Fully Depleted Silicon on Insulator Devices CMOS: The 28-nm Node Is the Perfect Technology for Analog, RF, mmW, and Mixed-Signal System-on-Chip Integration

2017 ◽  
Vol 9 (4) ◽  
pp. 18-26 ◽  
Author(s):  
Andreia Cathelin
Keyword(s):  
System On Chip ◽  
Silicon On Insulator ◽  
Signal System ◽  
Mixed Signal ◽  
Fully Depleted ◽  
On Chip ◽  
28 Nm

MISSION LEVEL MODELING AND SIMULATION LANGUAGE FOR MIXED-SIGNAL SYSTEM-ON-CHIP DESIGN

2007 ◽  
Vol 16 (01) ◽  
pp. 15-28 ◽  
Author(s):  
BOJAN ANDJELKOVIĆ ◽  
VANCO LITOVSKI ◽  
VOLKER ZERBE
Keyword(s):  
Uniform Design ◽  
Environmental Parameters ◽  
System On Chip ◽  
System Level ◽  
Signal System ◽  
Mixed Signal ◽  
Operational Conditions ◽  
Mission System ◽  
Implementation Level ◽  
On Chip

Modern complex system design demands modeling on a high level of abstraction together with the system environment components. Such model enables mission level system simulation in the context of its operational conditions. Mission level design using hardware description language AleC++ is presented in this paper. It provides mission and system level verification of a mixed-signal system-on-chip. After validation at mission and system level, this language enables designers to replace some of the components with implementation level models to test and validate the system implementation at mission level. Also, the language provides modeling capabilities that give the designer an opportunity to analyze the influence of low-level technological and environmental parameters to the complete system behavior. In this way a uniform design framework is achieved from mission/system down to implementation level. The application of the language both for mission/system and implementation level modeling is illustrated by an example of the electronic compass.

Staggered Heterojunctions-Based Nanowire Tunneling Field-Effect Transistors for Analog/Mixed-Signal System-on-Chip Applications

NANO ◽  
2015 ◽  
Vol 10 (02) ◽  
pp. 1550027 ◽  
Author(s):  
Avik Chakraborty ◽  
Angsuman Sarkar
Keyword(s):  
Tunnel Junction ◽  
Field Effect ◽  
Field Effect Transistors ◽  
Cutoff Frequency ◽  
System On Chip ◽  
Signal System ◽  
Output Resistance ◽  
Mixed Signal ◽  
On Chip ◽  
Rf Performance

This paper presents the analog/RF performance for an III–V semiconductor-based staggered hetero-tunnel-junction n-type nanowire (NW) tunneling field effect transistor (n-TFET), for the first time. The device parameters for analog/mixed-signaling applications, such as transconductance (gm), transconductance-to-drive current ratio (gm/I DS ), output resistance (R out ), intrinsic gain and unity-gain cutoff frequency (fT) are studied for III–V based NW n-TFET, with the help of device simulator and compared with those for a similarly sized homojunction (HJ) NW n-TFET. The result reveals that the hetero-tunnel-junction n-TFETs outperform their HJ counterparts for analog/mixed-signal system-on-chip (SoC) applications.

Three-dimensional impedance engineering for mixed-signal system-on-chip applications

2006 ◽  
Author(s):  
Kyuchul Chong ◽  
Xi Zhang ◽  
King-Ning Tu ◽  
Daquan Huang ◽  
Mau-Chung Frank Chang ◽  
...  
Keyword(s):  
Three Dimensional ◽  
System On Chip ◽  
Signal System ◽  
Mixed Signal ◽  
On Chip

scholarly journals High-Speed Serializer for a 64 GS s<sup>−1</sup> Digital-to-Analog Converter in a 28 nm Fully-Depleted Silicon-on-Insulator CMOS Technology

2018 ◽  
Vol 16 ◽  
pp. 99-108
Author(s):  
Daniel Widmann ◽  
Markus Grözing ◽  
Manfred Berroth
Keyword(s):  
High Speed ◽  
Average Power ◽  
Silicon On Insulator ◽  
Output Stage ◽  
Fully Depleted ◽  
Data Rates ◽  
Average Power Consumption ◽  
Digital To Analog ◽  
On Chip ◽  
28 Nm

Abstract. An attractive solution to provide several channels with very high data rates of tens of Gbit s−1 for digital-to-analog converters (DACs) in arbitrary waveform generators (AWGs) is to use a high speed serializer in front of the DAC. As data sources, on-chip memories, digital signal processors or field-programmable gate arrays can be used. Here, we present a serializer consisting of a 19 channel 16:1 multiplexer (MUX) for output data rates up to 64 Gbit s−1 per channel and a low skew (∼ 8.8 ps) two-phase frequency divider and clock distribution network that is completely realized in static CMOS logic. The circuit is designed in a 28 nm Fully-Depleted Silicon-on-Insulator (FD-SOI) technology and will be used in an 8 bit 64 GS s−1 DAC between the on-chip memory and the DAC output stage. Due to a four bits unary and four bits binary segmentation, a 19 channel MUX is required. Simulations on layout level reveal a data-dependent peak-to-peak jitter of less than 1.8 ps at the output of one MUX channel with a total average power consumption of approximately 1.15 W of the whole MUX and clock network.

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