This paper proposes design and implementation of low power Delay Locked Loop Architecture, with dynamic Multiplexer based Phase Frequency Detector with minimum locking time. Clock and data recovery systems are employed to derive the clocking information to correctly decode the transmitted data at the receiver. Delay Locked Loop is one of the most important clock recovery systems. The DLL architecture is designed using Cadence Virtuoso 180nm Technology with 1.8V power supply. The proposed DLL with Multiplexer based phase frequency detector shows significant reduction in power dissipation by 10% compared to DLL designed using D-FF based PFD and achieves locking state within 10 clock cycles with minimum jitter of 4.84326ps, measured within clock frequency range of 100-250MHz.
Design and Implementation of Low Power Delay Locked Loop using Multiplexer Based Phase Frequency Detector
