Phase-frequency detector in QCA nanotechnology using novel flip-flop with reset terminal

2020 ◽  
Vol 10 (2) ◽  
pp. 111-118
Author(s):  
Hani Alamdar ◽  
Gholamreza Ardeshir ◽  
Mohammad Gholami
Keyword(s):  
Flip Flop ◽  
Phase Frequency Detector ◽  
Frequency Detector

scholarly journals Time Amplifier Based Bang-Bang Phase Frequency Detector in 0.18μm CMOS Technology

2019 ◽  
Vol 9 (1S3) ◽  
pp. 85-89
Keyword(s):  
Dead Zone ◽  
Cmos Technology ◽  
Maximum Frequency ◽  
Flip Flop ◽  
Phase Frequency Detector ◽  
Sense Amplifier ◽  
Time Amplifier ◽  
Frequency Detector ◽  
Cmos Implementation

A CMOS Implementation of Time amplifier (TA) based Bang-Bang Phase Frequency Detector (BBPFD) using Sense amplifier based flip flop (SAFF) is presented in this paper using 0.18μm CMOS technology. A time amplifier based on feedback output generator concept is utilized in minimizing the metastability and increasing the gain of TA which in turn boosts the gain of Phase Frequency Detector (PFD). Also, a modified SAFF was built in CMOS 0.18μm technology at 1.8V which further reduces the hysteresis and metastability aspect related to PFD. The proposed PFD works at a maximum frequency of 4GHz consuming 0.46mW of power with no dead zone.

Design a Phase Frequency Detector

2013 ◽  
Vol 380-384 ◽  
pp. 3198-3203
Author(s):  
Xue Mei Lei ◽  
Xiao Dong Xing ◽  
Xue Dong Ding
Keyword(s):  
Power Consumption ◽  
Core Area ◽  
Operating Frequency ◽  
Cmos Process ◽  
Flip Flop ◽  
Phase Frequency Detector ◽  
High Frequencies ◽  
The Core ◽  
Input Signals ◽  
Frequency Detector

This paper describes a phase frequency detector application using 0.18μm CMOS process. In order to cover the high frequencies of input signals, TSPC D flip-flop structure are applied. The core area of proposal phase frequency detector is 60 μm×50 μm. The simulating results show that rang of operating frequency is from 500kHz to 500MHz and the power consumption is 0.722mW under a 1.8V supply.

scholarly journals Implementation of Phase Frequency Detector in Phase locked loop using Preset able modified TSPC D flip-flop

2019 ◽  
Vol 8 (12) ◽  
pp. 977-980
Keyword(s):  
Power Consumption ◽  
High Speed ◽  
Single Phase ◽  
Phase Locked Loop ◽  
Frequency Multiplier ◽  
Flip Flop ◽  
Phase Frequency Detector ◽  
Technology Applications ◽  
Phase Clock ◽  
Frequency Detector

Phase locked loop (PLL) forms an important part in many applications. Here design of PLL for frequency multiplier operation is considered. Frequency multiplier operation is implemented by using Preset able Modified Single Phase Clock (MTSPC) D flipflop logic circuits in Phase Frequency Detector (PFD). Preset able Modified Single Phase Clock (MTSPC) D flipflops functions at high speed with less power consumption. Noises in the form of glitches are introduced when a preset-able true single phase clocked D flipflop (TSPC) used in Phase Locked Loop. Preset-able modified TSPC (MTSPC) D flipflop used to overcome these glitches caused due to toggling at the output by use of PMOS. Technology applied is 90nm technology. Applications where better speed and reduced power consumption are required, this type of Phase locked loop (PLL) can be utilized.

Effect of Scaling on Phase Frequency Detector

2016 ◽  
Vol 7 (1) ◽  
pp. 20
Author(s):  
GULIHAR LATIKA ◽  
KRISHAN BAL ◽  
◽  
Keyword(s):  
Phase Frequency Detector ◽  
Frequency Detector

МАКРОМОДЕЛИРОВАНИЕ СХЕМЫ ФАПЧ С ИСПОЛЬЗОВАНИЕМ ПОЛНОЙ ПРИНЦИПИАЛЬНОЙ СХЕМЫ ФАЗОВОГО ДЕТЕКТОРА

2020 ◽  
Vol 96 (3s) ◽  
pp. 295-299
Author(s):  
М.М. Гурарий ◽  
М.М. Жаров ◽  
Л.П. Ионов ◽  
И.И. Мухин ◽  
С.Г. Русаков ◽  
...  
Keyword(s):  
Electric Circuit ◽  
Schematic Diagram ◽  
Equivalent Electric Circuit ◽  
Phase Frequency Detector ◽  
Frequency Detector ◽  
A Current

В работе рассмотрены проблемы анализа схем ФАПЧ с учетом наличия неидеальностей в схеме частотно-фазового детектора с токовым ключом. Для снижения затрат на моделирование предложено использовать эквивалентную электрическую схему, содержащую полную принципиальную схему ЧФД и схемные эквиваленты макромоделей остальных блоков ФАПЧ. The paper considers the problems of analyzing the PLL circuit taking into account the presence of nonidealities in the phase-frequency detector with a current key. To reduce the simulation efforts, it has been proposed to apply an equivalent electric circuit containing the complete schematic diagram of the PFD and circuit equivalents of the macromodels of other PLL blocks.

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