The 3D integrated circuits are enlarging the technology with lots of potentials which establish vertical interconnection between different dies or layers. In 3D-integrated circuit fabrication, congestion, and wirelength minimization are challenging processes. To overcome these problems, we proposed a novel optimization approach for useful partitioning, placement, and routing. Our proposed work consists of four significant stages, including partitioning, placement, routing, and fault diagnosis in through silicon via and spare through silicon via allocation. Firstly, the QuadTree partitioning method executed by the partitioning process. QuadTree method partitions the layer into four subdivisions and remains until it finds no space for partitioning. AND logic is proposed to overcome the congestion problem during placement. In the second stage, the functioning of the hybrid particle swarm optimization and simulated annealing algorithm proposed by the placement process. Particle swarm optimization computes fitness function for six constraints, specifically wirelength, area, power, cross talk, temperature, and delay. The simulated annealing places circuits in the specified area with the computed fitness function. In every 45°, Kruskal’s based octi-linear Steiner tree algorithm that establishes routes performs the routing by the third stage. In the last stage, fault detection in through silicon via and spare through silicon via allocation processes are executed using the support vector machine algorithm and dedicated switch. Support vector machine classifies the TSV into two, which includes regular and redundant through silicon via. The spare through silicon via allocation performed by using a dedicated switch. Finally, the proposed work evaluated based on metrics such as wire length, area, temperature, delay, and run time.
Through-silicon via stress characteristics and reliability impact on 3D integrated circuits
