Efficiency-based power MOSFETs size optimization method for DC-DC buck converters

Author(s):  
Wanjin Wang ◽  
Rongshan Wei ◽  
Yadong Yin
Author(s):  
Zhijun Liu ◽  
Shingo Cho ◽  
Akihiro Takezawa ◽  
Xiaopeng Zhang ◽  
Mitsuru Kitamura

2008 ◽  
Vol 2008 ◽  
pp. 1-9 ◽  
Author(s):  
Yali Xiong ◽  
Xu Cheng ◽  
Xiangcheng Wang ◽  
Pavan Kumar ◽  
Lina Guo ◽  
...  

This paper investigates the performance perspectives and theoretical limitations of trench power MOSFETs in synchronous rectifier buck converters operating in the MHz frequency range. Several trench MOSFET technologies are studied using a mixed-mode device/circuit modeling approach. Individual power loss contributions from the control and synchronous MOSFETs, and their dependence on switching frequency between 500 kHz and 5 MHz are discussed in detail. It is observed that the conduction loss contribution decreases from 40% to 4% while the switching loss contribution increases from 60% to 96% as the switching frequency increases from 500 KHz to 5 MHz. Beyond 1 MHz frequency there is no obvious benefit to increase the die size of either SyncFET or CtrlFET. The RDS(ON)×QG figure of merit (FOM) still correlates well to the overall converter efficiency in the MHz frequency range. The efficiency of the hard switching buck topology is limited to 80% at 2 MHz and 65% at 5 MHz even with the most advanced trench MOSFET technologies.


2021 ◽  
Vol 11 (23) ◽  
pp. 11449
Author(s):  
Pierandrea Dal Fabbro ◽  
Stefano Rosso ◽  
Alessandro Ceruti ◽  
Diego Boscolo Bozza ◽  
Roberto Meneghello ◽  
...  

An important issue when designing conformal lattice structures is the geometric modeling and prediction of mechanical properties. This paper presents suitable methods for obtaining optimized conformal lattice structures and validating them without the need for high computational power and time, enabling the designer to have quick feedback in the first design phases. A wireframe modeling method based on non-uniform rational basis spline (NURBS) free-form deformation (FFD) that allows conforming a regular lattice structure inside a design space is presented. Next, a previously proposed size optimization method is adopted for optimizing the cross-sections of lattice structures. Finally, two different commercial finite element software are involved for the validation of the results, based on Euler–Bernoulli and Timoshenko beam theories. The findings highlight the adaptability of the NURBS-FFD modeling approach and the reliability of the size optimization method, especially in stretching-dominated cell topologies and load conditions. At the same time, the limitation of the structural beam analysis when dealing with thick beams is noted. Moreover, the behavior of different kinds of lattices was investigated.


2013 ◽  
Vol 712-715 ◽  
pp. 2906-2912
Author(s):  
Kun Cai ◽  
Hong Yang He ◽  
Xin Huan Li ◽  
Yan Li

A hydraulic steel radial gate (SRG) with two oblique arms is designed by using topology optimization and size optimization. Topology and size optimization are carried out by using CAD software, e.g., Hyperworks. In the current design, the SRG is initially considered to have three main components, i.e., the arms, the supporting frame of arms and a panel for water retaining. To give a better design of these components, e.g., arms and its supporting frame, topology optimization is adopted. By topology optimization method, the shape of arm and the supporting frame are obtained. As construction of the new SRG is reconstructed by the components obtained, the stiffness, strength and stability of the new SRG is checked and some sizes of components in SRG are readjusted by using size optimization. The final design of the SRG is around 24% lighter than the traditional design whilst the safety of the new design is much better.


Author(s):  
Ian Kearney

Abstract Accurate and lossless current sensing is vital for high performance multiphase buck converters used in the latest voltage regulation modules (VRMs). A synchronous FET onstate resistance based approach is an alternative topology to DCR based sensing and is compatible with any controller, which requires inductor current information. The MOSFET driver has built-in sense circuitry, which when co-packaged with the MOSFETs reduces total footprint and ease of design. The Powerstage embodiment virtually eliminates the parasitic inductance and resistance between Control and Synchronous power MOSFETS; and using thick copper clips substantially reduce the parasitics associated with the input supply voltage (VIN) and the switch node output voltage (VSW) connections when compared to wire-bonded solutions. This paper presents a novel investigation into a contradictory low on-resistance paradox in a stacked 3D configuration. Through analysis, characterization and simulation the author deciphered the conundrum leading to a root cause explained by a mismatch of internal gain and referenced on-resistance. Building on previous metrology improvements the innovative insights drove analysis toward root-cause.


2006 ◽  
Vol 20 (25n27) ◽  
pp. 4099-4104 ◽  
Author(s):  
YOUNG-SHIN LEE ◽  
HYUN-SEUNG LEE ◽  
YOUNG-JIN CHOI ◽  
SEONG-WOO BYUN ◽  
WEOL-TAE KIM

A LCD glass plate is supported by multi-pins and golf-tee type support. In the FEM analysis, the support condition is treated as a simply supported boundary condition. In this study, the optimization on the location of multi-simply support is conducted. The size optimization method of ANSYS 8.0 is used as the optimization tool to search for the optimal support location of LCD glass plate. In the manufacturing process, the support condition is a fatal factor of quality control of LCD production. From the results of optimization, deflection decreases 51% compared with the original model.


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