Multi-Gb/s OOK mm-wave modulator ICs on 28 nm low-power digital CMOS

2016 ◽  
Author(s):  
Jan Dirk Leufker ◽  
David Fritsche ◽  
Guido Belfiore ◽  
Corrado Carta ◽  
Frank Ellinger
Keyword(s):  
Low Power ◽  
Digital Cmos ◽  
28 Nm

Millimeter-Wave Low-Noise Amplifier Design in 28-nm Low-Power Digital CMOS

2015 ◽  
Vol 63 (6) ◽  
pp. 1910-1922 ◽  
Author(s):  
David Fritsche ◽  
Gregor Tretter ◽  
Corrado Carta ◽  
Frank Ellinger
Keyword(s):  
Low Power ◽  
Millimeter Wave ◽  
Low Noise ◽  
Low Noise Amplifier ◽  
Digital Cmos ◽  
Amplifier Design ◽  
Noise Amplifier ◽  
28 Nm

Design and Characterization of a 3-bit 24-GS/s Flash ADC in 28-nm Low-Power Digital CMOS

2016 ◽  
Vol 64 (4) ◽  
pp. 1143-1152 ◽  
Author(s):  
Gregor Tretter ◽  
Mohammad Mahdi Khafaji ◽  
David Fritsche ◽  
Corrado Carta ◽  
Frank Ellinger
Keyword(s):  
Low Power ◽  
Digital Cmos ◽  
Flash Adc ◽  
28 Nm

scholarly journals The Demonstration of S2P (Serial-to-Parallel) Converter with Address Allocation Method Using 28 nm CMOS Technology

2021 ◽  
Vol 11 (1) ◽  
pp. 429
Author(s):  
Min-Su Kim ◽  
Youngoo Yang ◽  
Hyungmo Koo ◽  
Hansik Oh
Keyword(s):  
Integrated Circuits ◽  
Embedded System ◽  
Low Power ◽  
High Speed ◽  
Cmos Technology ◽  
Clock Frequency ◽  
Clock Generation ◽  
Allocation Method ◽  
Evaluation Board ◽  
28 Nm

To improve the performance of analog, RF, and digital integrated circuits, the cutting-edge advanced CMOS technology has been widely utilized. We successfully designed and implemented a high-speed and low-power serial-to-parallel (S2P) converter for 5G applications based on the 28 nm CMOS technology. It can update data easily and quickly using the proposed address allocation method. To verify the performances, an embedded system (NI-FPGA) for fast clock generation on the evaluation board level was also used. The proposed S2P converter circuit shows extremely low power consumption of 28.1 uW at 0.91 V with a core die area of 60 × 60 μm2 and operates successfully over a wide clock frequency range from 5 M to 40 MHz.

A 6-bit 1.2-GS/s low-power flash-ADC in 0.13-/spl mu/m digital CMOS

2005 ◽  
Vol 40 (7) ◽  
pp. 1499-1505 ◽  
Author(s):  
C. Sandner ◽  
M. Clara ◽  
A. Santner ◽  
T. Hartig ◽  
F. Kuttner
Keyword(s):  
Low Power ◽  
Digital Cmos ◽  
Flash Adc

Design Methodologies for Low-Power CMOS Operational Amplifiers in a 0.25¿m Digital CMOS Process

2006 ◽  
Author(s):  
Alfonso Cesar B. Albason ◽  
Neil Michael L. Axalan ◽  
Maria Theresa A. Gusad ◽  
John Richard E. Hizon ◽  
Marc D. Rosales
Keyword(s):  
Low Power ◽  
Operational Amplifiers ◽  
Cmos Process ◽  
Digital Cmos ◽  
Design Methodologies ◽  
Low Power Cmos ◽  
Cmos Operational Amplifiers

Low‐power 10‐bit 100 MS/s pipelined ADC in digital CMOS technology

2017 ◽  
Vol 11 (6) ◽  
pp. 589-596 ◽  
Author(s):  
Anil Singh ◽  
Veena Rawat ◽  
Alpana Agarwal
Keyword(s):  
Low Power ◽  
Cmos Technology ◽  
Pipelined Adc ◽  
Digital Cmos
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