A new conduction mechanism for the anomalous cells in thin oxide flash EEPROMs

Author(s):  
A. Modelli ◽  
F. Gilardoni ◽  
D. Ielmini ◽  
A.S. Spinelli
2003 ◽  
Vol 86 (3) ◽  
pp. 21-27
Author(s):  
Kenji Komiya ◽  
Takashi Oka ◽  
Naoki Okada ◽  
Yasuhisa Omura

1996 ◽  
Vol 17 (2) ◽  
pp. 56-58 ◽  
Author(s):  
N. Matsuo ◽  
H. Fujiwara ◽  
T. Miyoshi ◽  
T. Koyanagi

Author(s):  
Vinod Narang ◽  
P. Muthu ◽  
J.M. Chin ◽  
Vanissa Lim

Abstract Implant related issues are hard to detect with conventional techniques for advanced devices manufactured with deep sub-micron technology. This has led to introduction of site-specific analysis techniques. This paper presents the scanning capacitance microscopy (SCM) technique developed from backside of SOI devices for packaged products. The challenge from backside method includes sample preparation methodology to obtain a thin oxide layer of high quality, SCM parameters optimization and data interpretation. Optimization of plasma etching of buried oxide followed by a new method of growing thin oxide using UV/ozone is also presented. This oxidation method overcomes the limitations imposed due to packaged unit not being able to heat to high temperature for growing thermal oxide. Backside SCM successfully profiled both the n and p type dopants in both cache and core transistors.


2018 ◽  
Vol 93 (5) ◽  
pp. 603-610 ◽  
Author(s):  
Samia Mathlouthi ◽  
Abderrazek Oueslati ◽  
Bassem Louati

Nanomaterials ◽  
2021 ◽  
Vol 11 (6) ◽  
pp. 1401
Author(s):  
Te Jui Yen ◽  
Albert Chin ◽  
Vladimir Gritsenko

Large device variation is a fundamental challenge for resistive random access memory (RRAM) array circuit. Improved device-to-device distributions of set and reset voltages in a SiNx RRAM device is realized via arsenic ion (As+) implantation. Besides, the As+-implanted SiNx RRAM device exhibits much tighter cycle-to-cycle distribution than the nonimplanted device. The As+-implanted SiNx device further exhibits excellent performance, which shows high stability and a large 1.73 × 103 resistance window at 85 °C retention for 104 s, and a large 103 resistance window after 105 cycles of the pulsed endurance test. The current–voltage characteristics of high- and low-resistance states were both analyzed as space-charge-limited conduction mechanism. From the simulated defect distribution in the SiNx layer, a microscopic model was established, and the formation and rupture of defect-conductive paths were proposed for the resistance switching behavior. Therefore, the reason for such high device performance can be attributed to the sufficient defects created by As+ implantation that leads to low forming and operation power.


2021 ◽  
Vol 32 (18) ◽  
pp. 23232-23245
Author(s):  
Ishpal Rawal ◽  
Vipin Kumar ◽  
Vinod Kumar ◽  
Prikshit Gautam ◽  
Vijay Kumar Sharma
Keyword(s):  

2008 ◽  
Vol 1091 ◽  
Author(s):  
Hung-Keng Chen ◽  
Po-Tsun Liu ◽  
Ting-Chang Chang ◽  
S.-L. Shy

AbstractVariable temperature electrical measurement is well-established and used for determining the conduction mechanism in semiconductors. There is a Meyer¡VNeldel relationship between the activation energy and the prefactor with a Meyer¡VNeldel energy of 30.03 meV, which corresponds well with the isokinetic temperature of about 350 K. Therefore, the multiple trapping and release model is properly used to explain the thermally activated phenomenon. By the method, an exponential distribution of traps is assumed to be a better representation of trap states in band tail. Samples with higher temperature during measurement are observed to show better mobility, higher on-current and lower resistance, which agree well with the multiple trapping and release model proposed to explain the conduction mechanism in pentacene-based OTFTs.


Sign in / Sign up

Export Citation Format

Share Document