Statistical electro-thermal analysis with high compatibility of leakage power models

2010 ◽  
Author(s):  
Huai-Chung Chang ◽  
Pei-Yu Huang ◽  
Ting-Jung Li ◽  
Yu-Min Lee
Keyword(s):  
Thermal Analysis ◽  
Leakage Power ◽  
Power Models

Transistor Resizing Based Low Power Thermal Aware Adder Design on FPGA

2015 ◽  
Vol 1098 ◽  
pp. 37-43
Author(s):  
Kartik Kalia ◽  
Khyati Nanda ◽  
Arushi Aggarwal ◽  
Akshita Goel ◽  
Shivani Malhotra
Keyword(s):  
Thermal Analysis ◽  
Ambient Temperature ◽  
Heat Sink ◽  
Energy Efficient ◽  
Leakage Power ◽  
Junction Temperature ◽  
Efficient Technology ◽  
Scale Down ◽  
Energy Efficient Technology ◽  
Target Design

In this work, we are going to search the most thermal and energy efficient technology among 90nm, 65nm, 45nm, 40nm and 38nm technology based FPGA, and also searching the most thermal and energy efficient airflow, and heat sink profile. We are also doing thermal analysis for 273.15K-343.15K temperature. we are getting 31.67%, 75.71%, reduction in leakage power for 250LFM and 58.53%, 75.71% reduction in leakage power for 500LFM when we scale down ambient temperature from 343.15K to 283.15K for 65nm, 28nm technology based FPGA. There is 84.54%, 85.65%, reduction in junction temperature for 250LFM, 84.90%, 85.65%, reduction in junction temperature for 500LFM when we scale down ambient temperature from 343.15K to 283.15K for 65nm, 28nm technology based FPGA. In this work, we are using 90nm Spartan-3E FPGA, 65nm Virtex-5 FPGA, 45nm Spartan-6 FPGA, 40nm Virtex-6 FPGA, and 28nm Artix-7 FPGA. We are taking two different airflow of 250LFM and 500LFM. LFM is a unit of airflow. LFM is linear feet per minute. Adder is our target design.

scholarly journals Static Power Research on Nano Cryptographic Circuits

2019 ◽  
Vol 8 (2S3) ◽  
pp. 1241-1245
Keyword(s):  
Integrated Circuits ◽  
Analytical Model ◽  
Integrated Circuit ◽  
Data Security ◽  
Power Loss ◽  
Power Analysis ◽  
Leakage Power ◽  
Secret Key ◽  
Power Models ◽  
Static Power

In this present static power analysis of Nano circuit is presented. The attack is bused to obtain the secret key of a cryptographic core by measuring static power loss. These attack take leakage current from the integrated circuit depends upon input to extract secrete key called as Leakage Power Analysis (LPA) Since the leakage power expands a lot quicker than the dynamic power at each new innovation age, LPA assaults are a genuine risk to the data security of cryptographic circuits in sub-100-nm advancements. In this paper a leakage power attack is well demonstrated and simulated on different integrated circuits and an analytical model of LPA attack is presented to understand the effectiveness of this technique as a threat to cryptographic integrated circuits . The effect of innovation scaling is expressly tended to by methods for a straightforward analytical model and Monte Carlo simulation. Simulation on a 45nm, 65-and 90-nm technology and trial-experimental results are introduced to legitimize the suppositions and approve the leakage power models

THERMAL IMPACTS OF LEAKAGE POWER IN 2D/3D FLOORPLANNING

2010 ◽  
Vol 19 (07) ◽  
pp. 1483-1495
Author(s):  
YUCHUN MA ◽  
QIANG ZHOU ◽  
PINGQIANG ZHOU ◽  
XIANLONG HONG
Keyword(s):  
Thermal Analysis ◽  
Leakage Power ◽  
Total Power ◽  
Technology Scaling ◽  
Chip Temperature ◽  
Analysis Process ◽  
Design Challenge ◽  
Die Temperature ◽  
2D And 3D ◽  
The Impact

Leakage power is becoming a key design challenge in current and future CMOS designs. Due to technology scaling, the leakage power is rising so quickly that it largely elevates the die temperature. In this paper, we deeply investigate the impact of leakage power on thermal profile in both 2D and 3D floorplanning. Our results show that chip temperature can increase by about 11°C in 2D design and 68°C for 3D case with leakage power considered. Then we propose a thermal-driven floorplanning flow integrated with an iterative leakage-aware thermal analysis process to optimize chip temperature and save leakage power consumption. Experimental results show that for 2D design, the max chip temperature can be reduced by about 8°C and the proportion of leakage power to total power can be reduced from 19.17% to 11.12%. The corresponding results for 3D are 60°C temperature reduction and 16.3% less leakage power proportion.

I2C and HSTL IO Standard Based Low Power Thermal Aware Adder Design on 45nm FPGA

2015 ◽  
Vol 1098 ◽  
pp. 31-36 ◽  
Author(s):  
Kartik Kalia ◽  
Khyati Nanda ◽  
Arushi Aggarwal ◽  
Akshita Goel ◽  
Shivani Malhotra
Keyword(s):  
Thermal Analysis ◽  
Low Power ◽  
Ambient Temperature ◽  
Energy Efficient ◽  
Power Analysis ◽  
Leakage Power ◽  
Junction Temperature ◽  
Temperature Analysis ◽  
Target Design

In this work, we are we are going to search the most thermal and energy efficient IO Standards among the HSTL family and I2C family on 45 nm technology based FPGA. Here we are also doing thermal analysis for 273.15K-343.15K temperature, while during comparing the different IO Standards, we are taking the improvement level at 283.15K. In leakage power analysis, we are getting 9.09% improvement in HSTL with respect to others and in IO power analysis I2C shows 57.89% improvement with respect to others. In thermal analysis for maximum ambient temperature, we observe 1.79% improvement in HSTL_II as compared to others and in Junction Temperature analysis HSTL_I and I2C are 3.6% efficient than others. HSTL_I has minimum Theta Junction to Ambient Temperature value. In this work, we are using 45nm Spartan-6 FPGA. . We are taking airflow of 250LFM where LFM is a unit of airflow. LFM is linear feet per minute. Adder is our target design.

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