Codes for Error Correction in High-Speed Memory Systems—Part I: Correction of Cell Defects in Integrated Memories

1971 ◽  
Vol C-20 (8) ◽  
pp. 882-888 ◽  
Author(s):  
C.V. Srinivasan
Keyword(s):  
Error Correction ◽  
High Speed ◽  
Memory Systems

Compact and High-Speed Hsiao-Based SEC-DED Codec for Cache Memory

2021 ◽  
pp. 2250004
Author(s):  
Jagannath Samanta ◽  
Akash Kewat
Keyword(s):  
Error Correction ◽  
Error Detection ◽  
High Speed ◽  
Memory Systems ◽  
Cache Memory ◽  
Error Correction Codes ◽  
Parity Check Matrix ◽  
Single Error ◽  
Check Matrix ◽  
Field Programmable

Recently, there have been continuous rising interests of multi-bit error correction codes (ECCs) for protecting memory cells from soft errors which may also enhance the reliability of memory systems. The single error correction and double error detection (SEC-DED) codes are generally employed in many high-speed memory systems. In this paper, Hsiao-based SEC-DED codes are optimized based on two proposed optimization algorithms employed in parity check matrix and error correction logic. Theoretical area complexity of SEC-DED codecs require maximum 49.29%, 18.64% and 49.21% lesser compared to the Hsiao codes [M. Y. Hsiao, A class of optimal minimum odd-weight-column SEC-DED codes, IBM J. Res. Dev. 14 (1970) 395–401], Reviriego et al. codes [P. Reviriego, S. Pontarelli, J. A. Maestro and M. Ottavi, A method to construct low delay single error correction codes for protecting data bits only, IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst. 32 (2013) 479–483] and Liu et al. codes [S. Liu, P. Reviriego, L. Xiao and J. A. Maestro, A method to recover critical bits under a double error in SEC-DED protected memories, Microelectron. Reliab. 73 (2017) 92–96], respectively. Proposed codec is designed and implemented both in field programmable gate array (FPGA) and ASIC platforms. The synthesized SEC-DED codecs need 31.14% lesser LUTs than the original Hsiao code. Optimized codec is faster than the existing related codec without affecting its power consumption. These compact and faster SEC-DED codecs are employed in cache memory to enhance the reliability.

scholarly journals Study on the Implementation of a Simple and Effective Memory System for an AI Chip

Electronics ◽  
2021 ◽  
Vol 10 (12) ◽  
pp. 1399
Author(s):  
Taepyeong Kim ◽  
Sangun Park ◽  
Yongbeom Cho
Keyword(s):  
High Speed ◽  
Memory Systems ◽  
Memory System ◽  
External Memory ◽  
Essential Factor ◽  
Wide Bandwidth ◽  
Reading And Writing ◽  
Data Skew ◽  
Lower Performance ◽  
Efficient Memory

In this study, a simple and effective memory system required for the implementation of an AI chip is proposed. To implement an AI chip, the use of internal or external memory is an essential factor, because the reading and writing of data in memory occurs a lot. Those memory systems that are currently used are large in design size and complex to implement in order to handle a high speed and a wide bandwidth. Therefore, depending on the AI application, there are cases where the circuit size of the memory system is larger than that of the AI core. In this study, SDRAM, which has a lower performance than the currently used memory system but does not have a problem in operating AI, was used and all circuits were implemented digitally for simple and efficient implementation. In particular, a delay controller was designed to reduce the error due to data skew inside the memory bus to ensure stability in reading and writing data. First of all, it verified the memory system based on the You Only Look Once (YOLO) algorithm in FPGA to confirm that the memory system proposed in AI works efficiently. Based on the proven memory system, we implemented a chip using Samsung Electronics’ 65 nm process and tested it. As a result, we designed a simple and efficient memory system for AI chip implementation and verified it with hardware.

scholarly journals Economic Growth and Unemployment Nexus in USA

2019 ◽  
Vol 8 (4) ◽  
pp. 1317-1325
Keyword(s):  
Growth Rate ◽  
Error Correction ◽  
Unemployment Rate ◽  
High Speed ◽  
Empirical Relationship ◽  
Var Model ◽  
Output Gap ◽  
Causality Test ◽  
Vector Error Correction ◽  
Vector Error

Empirical relationship between unemployment and growth is not pronounced as we investigate the economic scenario of the nations. Author attempted to relate US unemployment rate to the growth during 1948-2016 by using bivariate and log regression models, Bai-Perron Model, Granger Causality test, Johansen cointegration test, vector auto regression and vector error correction models. Even, author also verified relationship between unemployment gap, output gap and growth in USA during the same period. Data on US unemployment rate, GDP and growth rate have been taken from Bureau of US census during 1948-2016. Data on US natural rate of unemployment was taken from Fed Bank of St.Louis from 1949 to 2016.The paper concludes that US unemployment rate is increasing at the rate of 0.507 per cent per annum and it has upward structural break in 1971.The nexus follows the Okun’s law in USA. US unemployment is negatively related with growth rate during 1948-2016.Their relationships are causal and cointegrated. VAR model is stable and stationary. Residual test showed non-normality and autocorrelations.Moreover, author showed negative relation between growth and unemployment gap in USA during 1949-2016.They have no causality and cointegration. Their VAR model is stable and stationary. The residual test proved non-normality and auto-correlation problems. Perceptible output gap influences unemployment gap negatively during 1949-2016 .It has significant bi-directional causality and one cointegrating equation. In Vector error correction model, error corrections are significant with high speed having stability, autocorrelation and non-normality. The rate of decline in unemployment rate due to increased growth rate in USA during 1948-2016 was marginal.

Research on error-correction algorithm of high-speed QKD system based on FPGA

2019 ◽  
Vol 17 (02) ◽  
pp. 1950013
Author(s):  
Shi-Biao Tang ◽  
Jie Cheng
Keyword(s):  
Error Correction ◽  
Quantum Key Distribution ◽  
High Speed ◽  
Information Leakage ◽  
Correction Algorithm ◽  
Performance Limit ◽  
Performance Requirement ◽  
The Future ◽  
Field Programmable ◽  
Error Correction Algorithm

In the process of quantum key distribution (QKD), error correction algorithm is used to correct the error bits of the key at both ends. The existing applied QKD system has a low key rate and is generally Kbps of magnitude. Therefore, the performance requirement of data processing such as error correction is not high. In order to cope with the development demand of high-speed QKD system in the future, this paper introduces the Winnow algorithm to realize high-speed parity and hamming error correction based on Field Programmable Gate Array (FPGA), and explores the performance limit of this algorithm. FPGA hardware implementation can achieve the scale of Mbps bandwidth, with choosing different group length of sifted key by different error rate, and can achieve higher error correction efficiency by reducing the information leakage in the process of error correction, and improves the QKD system’s secure key rate, thus helping the future high-speed QKD system.

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