Wafer-Level Packaging Design With Through Substrate Grooves as Interconnection for GaAs-Based Image Sensor

2013 ◽  
Vol 3 (12) ◽  
pp. 2022-2028 ◽  
Author(s):  
Shuangfu Wang ◽  
Jiaotuo Ye ◽  
Gaowei Xu ◽  
Le Luo
Keyword(s):  
Image Sensor ◽  
Wafer Level ◽  
Packaging Design ◽  
Wafer Level Packaging

300mm Scaling of Critical Silicon Etches for Image Sensor Wafer-Level Packaging Based on Tessera's MVP (TSV) Technology

2011 ◽  
Vol 2011 (DPC) ◽  
pp. 002254-002271
Author(s):  
Dave Thomas ◽  
Matthew Muggeridge ◽  
Mike Steel ◽  
Dorleta Cortaberria Sanz ◽  
Hefin Griffiths ◽  
...  
Keyword(s):  
High Performance ◽  
Form Factors ◽  
Image Sensor ◽  
Electrical Performance ◽  
Depth Range ◽  
Back Side ◽  
Wafer Level ◽  
Wafer Level Packaging ◽  
Profile Control ◽  
Bond Pads

Miniature, high performance camera modules are found in a range of consumer devices including phones, PDAs, cameras and gaming consoles. According to Gartner the $1B image sensor market will grow to $2.3B by 2013. Image sensor packaging technologies are increasingly required to deliver greater reliability within smaller form factors. Tessera's OptiML™ Micro Via Pad (MVP) wafer-level packaging technology is in production on 200mm wafers. This paper will report on the first joint activity that scales this technology to 300mm. We focus on three critical silicon etches that form the back-bone of the structure. These etches are carried out from the wafer back-side while bonded to a glass carrier. First there is a blanket dry etch. This removes stress introduced by the back-grind. Uniformity control to < ±5% is essential for this process. Second, after a lithography step, tapered silicon trenches are etched forming streets to a certain depth. The trench etch uniformity is critical because it defines the depth range for the subsequent Vias. Profile control is needed to ease the subsequent spray-coat lithography. Lastly, vias are then etched down to metal bond pads on the device side of the wafer. CD and taper control is required here both within wafer and between wafers. End-pointing represents a way of ensuring process reproducibility. In 2010 Tessera carried out 300mm demos with key suppliers. As part of this activity SPTS scaled the above critical silicon etches. The wafers were further processed into functional die. We will describe the etch equipment used, report on the critical processes developed emphasizing the relationships between 200mm and 300mm results and the essential control parameters. We will also demonstrate successful scaling by including data on the electrical performance of packaged devices.

Wafer-Level Packaging Technology With Through-Hole Interconnections in Silicon Substrate

2005 ◽  
Author(s):  
Satoshi Yamamoto ◽  
Masanobu Saruta ◽  
Hideyuki Wada ◽  
Michikazu Tomita ◽  
Tatsuo Suemasu
Keyword(s):  
Image Sensor ◽  
Electrical Characteristics ◽  
Mems Devices ◽  
Wafer Level ◽  
Packaging Technology ◽  
Wafer Level Packaging ◽  
Advanced Packaging ◽  
Resistance Breakdown ◽  
Paper Fabrication ◽  
Through Hole

An advanced packaging technology with through-hole interconnections, which enables miniaturization and high-density packaging of electronic devices including MEMS devices and optical devices, has been developed. In this work, through-hole interconnections were applied to an image sensor packaging. Through-holes, 80μm in diameter and 200μm in depth, were formed from backside of the device wafer by Deep Reactive Ion Etching (DRIE). After an insulation layer was formed inside the holes, conductive material such as copper (Cu) or Gold-Tin (Au-Sn) alloy solder was filled into the holes by electroplating method or Molten Metal Suction Method (MMSM). This technology enables wafer-level packaging of the image sensor device. Some electrical characteristics and reliability performances including electric resistance, breakdown voltage, high-temperature storage test, heat cycle test, temperature-humidity test were examined. In this paper, fabrication processes, structural and electrical characteristics and reliability of the package will be reported.

CMOS image sensor wafer-level packaging

2011 ◽  
Author(s):  
Thorsten Matthias ◽  
Gerald Kreindl ◽  
Viorel Dragoi ◽  
Markus Wimplinger ◽  
Paul Lindner
Keyword(s):  
Cmos Image Sensor ◽  
Image Sensor ◽  
Wafer Level ◽  
Wafer Level Packaging

MEMS Wafer-level Packaging Technology Using LTCC Wafer

2012 ◽  
Vol 132 (8) ◽  
pp. 246-253 ◽  
Author(s):  
Mamoru Mohri ◽  
Masayoshi Esashi ◽  
Shuji Tanaka
Keyword(s):  
Wafer Level ◽  
Packaging Technology ◽  
Wafer Level Packaging

Development of Wafer Level Chip Size Packaging Process and its Application to the CMOS Image Sensor Module for Medical Device

2017 ◽  
Vol 137 (2) ◽  
pp. 48-58
Author(s):  
Noriyuki Fujimori ◽  
Takatoshi Igarashi ◽  
Takahiro Shimohata ◽  
Takuro Suyama ◽  
Kazuhiro Yoshida ◽  
...  
Keyword(s):  
Medical Device ◽  
Cmos Image Sensor ◽  
Image Sensor ◽  
Wafer Level ◽  
Packaging Process ◽  
Sensor Module ◽  
Chip Size

3D IC/Stacked Device Fault Isolation Using 3D Magnetic Field Imaging

2014 ◽  
Author(s):  
A. Orozco ◽  
N.E. Gagliolo ◽  
C. Rowlett ◽  
E. Wong ◽  
A. Moghe ◽  
...  
Keyword(s):  
Magnetic Field ◽  
Fault Isolation ◽  
Wafer Level ◽  
Wafer Level Packaging ◽  
Current Location ◽  
Geometrical Information ◽  
Magnetic Field Imaging ◽  
Silicon Vias ◽  
Non Destructive ◽  
Field Imaging

Abstract The need to increase transistor packing density beyond Moore's Law and the need for expanding functionality, realestate management and faster connections has pushed the industry to develop complex 3D package technology which includes System-in-Package (SiP), wafer-level packaging, through-silicon-vias (TSV), stacked-die and flex packages. These stacks of microchips, metal layers and transistors have caused major challenges for existing Fault Isolation (FI) techniques and require novel non-destructive, true 3D Failure Localization techniques. We describe in this paper innovations in Magnetic Field Imaging for FI that allow current 3D mapping and extraction of geometrical information about current location for non-destructive fault isolation at every chip level in a 3D stack.

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