Evaluation of insulation performance of polymeric surface using a novel separation technique of leakage current

2003 ◽  
Vol 10 (6) ◽  
pp. 1053-1060 ◽  
Author(s):  
M. Otsubo ◽  
T. Hashiguchi ◽  
C. Honda ◽  
O. Takenouchi ◽  
T. Sakoda ◽  
...  
2017 ◽  
Vol 137 (8) ◽  
pp. 481-486
Author(s):  
Junichi Hayasaka ◽  
Kiwamu Shirakawa ◽  
Nobukiyo Kobayashi ◽  
Kenichi Arai ◽  
Nobuaki Otake ◽  
...  

2010 ◽  
Vol 130 (11) ◽  
pp. 1037-1041 ◽  
Author(s):  
Takuma Miyake ◽  
Yuya Seo ◽  
Tatsuya Sakoda ◽  
Masahisa Otsubo
Keyword(s):  

2002 ◽  
Vol 716 ◽  
Author(s):  
Yi-Mu Lee ◽  
Yider Wu ◽  
Joon Goo Hong ◽  
Gerald Lucovsky

AbstractConstant current stress (CCS) has been used to investigate the Stress-Induced Leakage Current (SILC) to clarify the influence of boron penetration and nitrogen incorporation on the breakdown of p-channel devices with sub-2.0 nm Oxide/Nitride (O/N) and oxynitride dielectrics prepared by remote plasma enhanced CVD (RPECVD). Degradation of MOSFET characteristics correlated with soft breakdown (SBD) and hard breakdown (HBD), and attributed to the increased gate leakage current are studied. Gate voltages were gradually decreased during SBD, and a continuous increase in SILC at low gate voltages between each stress interval, is shown to be due to the generation of positive traps which are enhanced by boron penetration. Compared to thermal oxides, stacked O/N and oxynitride dielectrics with interface nitridation show reduced SILC due to the suppression of boron penetration and associated positive trap generation. Devices stressed under substrate injection show harder breakdown and more severe degradation, implying a greater amount of the stress-induced defects at SiO2/substrate interface. Stacked O/N and oxynitride devices also show less degradation in electrical performance compared to thermal oxide devices due to an improved Si/SiO2 interface, and reduced gate-to-drain overlap region.


2017 ◽  
Author(s):  
Seong-Sik Moon ◽  
Jinsoo Park ◽  
Gun Woo Kim ◽  
Seung-Jae Yoo ◽  
Gwang Hoon Rhee

Author(s):  
Franco Stellari ◽  
Peilin Song ◽  
James C. Tsang ◽  
Moyra K. McManus ◽  
Mark B. Ketchen

Abstract Hot-carrier luminescence emission is used to diagnose the cause of excess quiescence current, IDDQ, in a low power circuit implemented in CMOS 7SF technology. We found by optical inspection of the chip that the high IDDQ is related to the low threshold, Vt, device process and in particular to transistors with minimum channel length (0.18 μm). In this paper we will also show that it is possible to gain knowledge regarding the operating conditions of the IC from the analysis of optical emission due to leakage current, aside from simply locating defects and failures. In particular, we will show how it is possible to calculate the voltage drop across the circuit power grid from time-integrated acquisitions of leakage luminescence.


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