A 1.2 V, Highly Reliable RHBD 10T SRAM Cell for Aerospace Application

Abstract With shrinking feature size of integrated circuits traditional FA techniques like SEM inspection of top down delayered devices or cross sectioning often cannot determine the physical root cause. Inside SRAM blocks the aggressive design rules of transistor parameters can cause a local mismatch and therefore a soft fail of a single SRAM cell. This paper will present a new approach to identify a physical root cause with the help of nano probing and TCAD simulation to allow the wafer fab to implement countermeasures.

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Specification for spring retaining rings for aerospace application: carbon steel circlips (metric series)

10.3403/00010241u ◽

2015 ◽

Keyword(s):

Carbon Steel ◽

Aerospace Application

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Implementation and Determining Low Power Analysis of Various Structures of SRAM Cell

Third International Conference on Current Trends in Engineering Science and Technology ICCTEST-2017 ◽

10.21647/icctest/2017/48993 ◽

2017 ◽

Author(s):

T. R. Lakshmidevi

Keyword(s):

Low Power ◽

Power Analysis ◽

Sram Cell

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Robust Low Power 12T SRAM Cell Design based Full Adder using 120nm,90nm,65nm and 45nm Technologies

International Journal for Research in Applied Science and Engineering Technology ◽

10.22214/ijraset.2018.4060 ◽

2018 ◽

Vol 6 (4) ◽

pp. 332-340

Author(s):

Syed Mohammad Imran Ali

Keyword(s):

Low Power ◽

Full Adder ◽

Cell Design ◽

Sram Cell

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Analysis of 6T SRAM Cell in Different Technologies

Circulation in Computer Science ◽

10.22632/ccs-2017-mcsp026 ◽

2017 ◽

Vol MCSP2017 (01) ◽

pp. 7-10 ◽

Cited By ~ 2

Author(s):

Subhashree Rath ◽

Siba Kumar Panda

Keyword(s):

Low Power ◽

Data Storage ◽

Low Voltage ◽

Random Access ◽

Storage Device ◽

Cmos Process ◽

Process Technology ◽

Digital Devices ◽

Noise Margin ◽

Sram Cell

Static random access memory (SRAM) is an important component of embedded cache memory of handheld digital devices. SRAM has become major data storage device due to its large storage density and less time to access. Exponential growth of low power digital devices has raised the demand of low voltage low power SRAM. This paper presents design and implementation of 6T SRAM cell in 180 nm, 90 nm and 45 nm standard CMOS process technology. The simulation has been done in Cadence Virtuoso environment. The performance analysis of SRAM cell has been evaluated in terms of delay, power and static noise margin (SNM).

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