Short Circuit Failure Mechanisms of 650-V GaN/SiC Cascode Devices in Comparison with SiC MOSFETs

Author(s):  
Jiahui Sun ◽  
Kailun Zhong ◽  
Zheyang Zheng ◽  
Gang Lyu ◽  
Kevin J. Chen
2019 ◽  
Vol 100-101 ◽  
pp. 113454 ◽  
Author(s):  
C. Abbate ◽  
G. Busatto ◽  
A. Sanseverino ◽  
D. Tedesco ◽  
F. Velardi

2018 ◽  
Vol 57 (7) ◽  
pp. 074102 ◽  
Author(s):  
Masaki Namai ◽  
Junjie An ◽  
Hiroshi Yano ◽  
Noriyuki Iwamuro

2021 ◽  
Author(s):  
Juan Carlos Iglesias-Rojas

<div>Isolated multilevel inverters are widely used in renewable energy systems and industrial applications. Isolated IGBT topologies exploit the usage of low-frequency transformers that improve robustness and reliability. However, critical failure mechanisms should be considered at the design stage to ensure proper performance. This paper describes these critical failure mechanisms, such as short circuit, cross-conduction, IGBT high inductive load avalanche, IGBT second turn-on, VS-undershoot, transformer inrush current, IGBT thermal runaway, and cable switching interference. Furthermore, this paper comprises design techniques to prevent these failures. The previous failure mechanisms come from the inverter's power stage, except switching interference from control signal cables and directly affecting the control device functionality. This work also proposes a circuit topology based on FPGA resources to reduce switching interference from control signal cables. It behaves like a fault tolerant digital input that effectively filters bouncing events shorter than 2μs. Measurements report satisfactory experimental results upon constructing a 45kVA ac-side-isolated 13-level inverter.</div>


2007 ◽  
Vol 556-557 ◽  
pp. 779-782 ◽  
Author(s):  
Satoshi Tanimoto ◽  
Tatsuhiro Suzuki ◽  
Akihiro Hanamura ◽  
Masakatsu Hoshi ◽  
Toshiro Shinohara ◽  
...  

This paper discusses critical reliability issues and their countermeasures for vertically structured poly-Si gate n-channel power MOSFETs (DMOS) on 4H-SiC when operated at an elevated temperature of more than 300°C for a long period of time. Two destructive failures were identified in a storage life test at 500°C: a short-circuit between the source and the gate and a disconnection at the n+ source contact. The former was caused by interlayer dielectric erosion and/or Al spearing into the poly-Si gate; the latter was caused by the disappearance of the NiSix contact layer. Effective and practical countermeasures were devised and implemented. Device lifetime against the three different failure mechanisms was improved in every case by at least one order of magnitude.


Materials ◽  
2022 ◽  
Vol 15 (2) ◽  
pp. 598
Author(s):  
Yuan Zou ◽  
Jue Wang ◽  
Hongyi Xu ◽  
Hengyu Wang

In this paper, the short-circuit robustness of 1200 V silicon carbide (SiC) trench MOSFETs with different gate structures has been investigated. The MOSFETs exhibited different failure modes under different DC bus voltages. For double trench SiC MOSFETs, failure modes are gate failure at lower dc bus voltages and thermal runaway at higher dc bus voltages, while failure modes for asymmetric trench SiC MOSFETs are soft failure and thermal runaway, respectively. The shortcircuit withstanding time (SCWT) of the asymmetric trench MOSFET is higher than that of the double trench MOSFETs. The thermal and mechanical stresses inside the devices during the short-circuit tests have been simulated to probe into the failure mechanisms and reveal the impact of the device structures on the device reliability. Finally, post-failure analysis has been carried out to verify the root causes of the device failure.


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