scholarly journals Mitigation and Predictive Assessment of SET Immunity of Digital Logic Circuits for Space Missions

Aerospace ◽  
2020 ◽  
Vol 7 (2) ◽  
pp. 12 ◽  
Author(s):  
Ygor Q. Aguiar ◽  
Frédéric Wrobel ◽  
Jean-Luc Autran ◽  
Paul Leroux ◽  
Frédéric Saigné ◽  
...  
Keyword(s):  
System Integration ◽  
Space Station ◽  
Vlsi Circuits ◽  
Advanced Technology ◽  
Combinational Circuits ◽  
Single Event ◽  
Single Event Transient ◽  
Space Applications ◽  
Predictive Assessment ◽  
Technology Nodes

Due to the intrinsic masking effects of combinational circuits in digital designs, Single-Event Transient (SET) effects were considered irrelevant compared to the data rupture caused by Single-Event Upset (SEU) effects. However, the importance of considering SET in Very-Large-System-Integration (VLSI) circuits increases given the reduction of the transistor dimensions and the logic data path depth in advanced technology nodes. Accordingly, the threat of SET in electronics systems for space applications must be carefully addressed along with the SEU characterization. In this work, a systematic prediction methodology to assess and improve the SET immunity of digital circuits is presented. Further, the applicability to full-custom and cell-based design methodologies are discussed, and an analysis based on signal probability and pin assignment is proposed to achieve a more application-efficient SET-aware optimization of synthesized circuits. For instance, a SET-aware pin assignment can provide a reduction of 37% and 16% on the SET rate of a NOR gate for a Geostationary Orbit (GEO) and the International Space Station (ISS) orbit, respectively.

scholarly journals Investigation of Heavy-Ion Induced Single-Event Transient in 28 nm Bulk Inverter Chain

Symmetry ◽  
2020 ◽  
Vol 12 (4) ◽  
pp. 624
Author(s):  
Anquan Wu ◽  
Bin Liang ◽  
Yaqing Chi ◽  
Zhenyu Wu
Keyword(s):  
Integrated Circuits ◽  
Heavy Ions ◽  
Heavy Ion ◽  
High Energy ◽  
Advanced Technology ◽  
Sensitive Volume ◽  
Single Event ◽  
Space Applications ◽  
Order Of Magnitude ◽  
28 Nm

The reliability of integrated circuits under advanced process nodes is facing more severe challenges. Single-event transients (SET) are an important cause of soft errors in space applications. The SET caused by heavy ions in the 28 nm bulk silicon inverter chains was studied. A test chip with good symmetry layout design was fabricated based on the 28 nm process, and the chip was struck by using 5 kinds of heavy ions with different linear energy transfer (LET) values on heavy-ion accelerator. The research results show that in advanced technology, smaller sensitive volume makes SET cross-section measured at 28 nm smaller than 65 nm by an order of magnitude, the lower critical charge required to generate SET will increase the reliability threat of low-energy ions to the circuit, and high-energy ions are more likely to cause single-event multiple transient (SEMT), which cannot be ignored in practical circuits. The transients pulse width data can be used as a reference for SET modeling in complex circuits.

scholarly journals Application of PODEM Algorithm for Fault Detection and Location in FinFet based Combinational VLSI Circuits

2019 ◽  
Vol 9 (2) ◽  
pp. 236-241
Keyword(s):  
Fault Detection ◽  
Fault Location ◽  
Research Work ◽  
Vlsi Circuits ◽  
Test Vector ◽  
Combinational Circuits ◽  
Sensitive Test ◽  
Test Algorithm ◽  
Technology Nodes ◽  
Embedded Memories

FinFet transistors are used in major semiconductor organizations and a significant role is played by it in developing the silicon industries. Due to few embedded memories and other circuit issues the transistors have specific faults in manufacturing, designing of the circuit etc. This paper presents an advanced test algorithm to diagnose those faults. The circuit with different gates is designed to identify the places having faults. In addition, different algorithms such as PODEM (Path Oriented Decision Making algorithms) are used to find the fault detection and location. The Furthermore, more complicated circuits are analyzed for fault detection with different approach. In this research work Combinational Circuits are designed using 20nm/32nm technology nodes in LT Spice environment and PODEM Algorithm is implemented which is developed in MATLAB, to detect and identify fault location and sensitive test vector to detect fault in the circuit and results are presented..

scholarly journals Single-Event-Transient Resilient Memory for DSP in Space Applications

2018 ◽  
Author(s):  
Ne Kyaw Zwa Lwin ◽  
H. Sivaramakrishnan ◽  
Kwen-Siong Chong ◽  
Tong Lin ◽  
Wei Shu ◽  
...  
Keyword(s):  
Single Event ◽  
Single Event Transient ◽  
Space Applications

scholarly journals Integrated Silicon Photonics for Enabling Next-Generation Space Systems

Photonics ◽  
2021 ◽  
Vol 8 (4) ◽  
pp. 131
Author(s):  
George N. Tzintzarov ◽  
Sunil G. Rao ◽  
John D. Cressler
Keyword(s):  
Silicon Photonics ◽  
Radiation Effects ◽  
Space Systems ◽  
Single Event ◽  
Transient Effects ◽  
Single Event Transient ◽  
Space Applications ◽  
Silicon Waveguides ◽  
Current State ◽  
Integrated Silicon Photonics

A review of silicon photonics for space applications is presented. The benefits and advantages of size, weight, power, and cost (SWaP-C) metrics inherent to silicon photonics are summarized. Motivation for their use in optical communications systems and microwave photonics is addressed. The current state of our understanding of radiation effects in silicon photonics is included in this discussion. Total-ionizing dose, displacement damage, and single-event transient effects are discussed in detail for germanium-integrated photodiodes, silicon waveguides, and Mach-Zehnder modulators. Areas needing further study are suggested.

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