Signal and Noise Performance of a 110-nm CMOS Technology for Photon Science Applications

2019 ◽  
Vol 66 (4) ◽  
pp. 752-759
Author(s):  
Gianluca Traversi ◽  
Roberto Dinapoli ◽  
Massimo Manghisoni ◽  
Aldo Mozzanica ◽  
Elisa Riceputi
Keyword(s):  
Cmos Technology ◽  
Noise Performance ◽  
Photon Science

A LOW POWER AND VARIATION-INSENSITIVE CURRENT-MODE SIGNALING SCHEME

2013 ◽  
Vol 22 (08) ◽  
pp. 1350068
Author(s):  
XINSHENG WANG ◽  
YIZHE HU ◽  
LIANG HAN ◽  
JINGHU LI ◽  
CHENXU WANG ◽  
...  
Keyword(s):  
Low Power ◽  
High Speed ◽  
Current Mode ◽  
Signal Propagation ◽  
Cmos Technology ◽  
Propagation Delay ◽  
Noise Performance ◽  
On Chip ◽  
Variation Tolerance ◽  
Driving Signal

Process and supply variations all have a large influence on current-mode signaling (CMS) circuits, limiting their application on the fields of high-speed low power communication over long on-chip interconnects. A variation-insensitive CMS scheme (CMS-Bias) was offered, employing a particular bias circuit to compensate the effects of variations, and was robust enough against inter-die and intra-die variations. In this paper, we studied in detail the principle of variation tolerance of the CMS circuit and proposed a more suitable bias circuit for it. The CMS-Bias with the proposed bias circuit (CMS-Proposed) can acquire the same variation tolerance but consume less energy, compared with CMS-Bias with the original bias circuit (CMS-Original). Both the CMS schemes were fabricated in 180 nm CMOS technology. Simulation and measured results indicate that the two CMS interconnect circuits have the similar signal propagation delay when driving signal over a 10 mm line, but the CMS-Proposed offers about 9% reduction in energy/bit and 7.2% reduction in energy-delay-product (EDP) over the CMS-Original. Simulation results show that the two CMS schemes only change about 5% in delay when suffering intra-die variations, and have the same robustness against inter-die variations. Both simulation and measurements all show that the proposed bias circuits, employing self-biasing structure, contribute to robustness against supply variations to some extent. Jitter analysis presents the two CMS schemes have the same noise performance.

15 GHz quadrature voltage controlled oscillator in 130 nm CMOS technology

2011 ◽  
Vol 3 (6) ◽  
pp. 627-631 ◽  
Author(s):  
Paolo Lucchi ◽  
Davide Dermit ◽  
Gilles Jacquemod ◽  
Jean Baptiste Begueret ◽  
Mattia Borgarino
Keyword(s):  
Phase Noise ◽  
Phase Locked Loop ◽  
Cmos Technology ◽  
Voltage Controlled Oscillator ◽  
Noise Performance ◽  
Commercial Products ◽  
Satellite Applications ◽  
Phase Noise Performance

This paper reports a 15 GHz quadrature voltage controlled oscillator (QVCO) designed in a 130 nm CMOS technology. The phase noise performance of the QVCO and of a phase locked loop (PLL) where the QVCO was inserted were compared with the literature and with telecom standards and commercial products for broadcast satellite applications.

Fully Differential Difference Amplifier for Low-Noise and Low-Distortion Applications

2015 ◽  
Vol 25 (03) ◽  
pp. 1640019 ◽  
Author(s):  
Daniel Arbet ◽  
Gabriel Nagy ◽  
Martin Kováč ◽  
Viera Stopjaková
Keyword(s):  
Dynamic Range ◽  
High Dynamic Range ◽  
Cmos Technology ◽  
Low Noise ◽  
Noise Performance ◽  
Micro Electro Mechanical Systems ◽  
Differential Signal ◽  
Fully Differential ◽  
Differential Difference Amplifier ◽  
High Dynamic

In this paper, a fully differential difference amplifier (FDDA) designed in 0.35[Formula: see text][Formula: see text]m CMOS technology is presented. The proposed amplifier reaches high dynamic range (DR) and low input referred noise. Comparison of noise performance of the proposed FDDA to an ordinary differential amplifier has been performed. Achieved results prove that the developed amplifier circuit can be advantageously used in applications that require a fully differential signal. Then, simulation results have been verified by the measurement of prototyped chips. In our work, the proposed amplifier was experimentally employed in the analog frontend of the readout interface (RI) for a Micro-Electro-Mechanical-Systems (MEMS) capacitive microphone.

scholarly journals Two-Step Single Slope/SAR ADC with Error Correction for CMOS Image Sensor

2014 ◽  
Vol 2014 ◽  
pp. 1-6 ◽  
Author(s):  
Fang Tang ◽  
Amine Bermak ◽  
Abbes Amira ◽  
Mohieddine Amor Benammar ◽  
Debiao He ◽  
...  
Keyword(s):  
Power Consumption ◽  
Error Correction ◽  
Cmos Image Sensor ◽  
Cmos Technology ◽  
Image Sensor ◽  
Sar Adc ◽  
Quantization Noise ◽  
Noise Performance ◽  
Chip Area ◽  
Full Resolution

Conventional two-step ADC for CMOS image sensor requires full resolution noise performance in the first stage single slope ADC, leading to high power consumption and large chip area. This paper presents an 11-bit two-step single slope/successive approximation register (SAR) ADC scheme for CMOS image sensor applications. The first stage single slope ADC generates a 3-bit data and 1 redundant bit. The redundant bit is combined with the following 8-bit SAR ADC output code using a proposed error correction algorithm. Instead of requiring full resolution noise performance, the first stage single slope circuit of the proposed ADC can tolerate up to 3.125% quantization noise. With the proposed error correction mechanism, the power consumption and chip area of the single slope ADC are significantly reduced. The prototype ADC is fabricated using 0.18 μm CMOS technology. The chip area of the proposed ADC is 7 μm × 500 μm. The measurement results show that the energy efficiency figure-of-merit (FOM) of the proposed ADC core is only 125 pJ/sample under 1.4 V power supply and the chip area efficiency is 84 k μm2·cycles/sample.

scholarly journals RF CMOS Oscillators Design for autonomous Connected Objects

2019 ◽  
Vol 88 ◽  
pp. 05001
Author(s):  
Fayrouz Haddad ◽  
Wenceslas Rahajandraibe ◽  
Imen Ghorbel
Keyword(s):  
Performance Optimization ◽  
Tuning Range ◽  
Frequency Tuning ◽  
Cmos Technology ◽  
Voltage Controlled Oscillator ◽  
Noise Performance ◽  
Ultra Low Power ◽  
Wireless Transceiver ◽  
Cmos Oscillators ◽  
Phase Noise Performance

Voltage controlled oscillator (VCO) is an integral part of IoT wireless transceiver components. In this paper, VCOs operating around 2.4 GHz have been designed in CMOS technology. The relation between their components and specifications is studied for their performance optimization. Ultra-low power, less than 270 µW, has been obtained, while performing a frequency tuning range of about 10% between 2.1 and 2.4 GHz. Investigations on phase noise performance have been also achieved.

scholarly journals A PVT-Robust Super-Regenerative Receiver with Background Frequency Calibration and Concurrent Quenching Waveform

Electronics ◽  
2019 ◽  
Vol 8 (10) ◽  
pp. 1119 ◽  
Author(s):  
Yin ◽  
Fu ◽  
El-Sankary
Keyword(s):  
Data Stream ◽  
Input Data ◽  
Phase Error ◽  
Random Phase ◽  
High Sensitivity ◽  
Cmos Technology ◽  
Low Noise ◽  
Center Frequency ◽  
Noise Performance ◽  
Frequency Calibration

A process-voltage-temperature (PVT)-robust, low power, low noise, and high sensitivity, super-regenerative (SR) receiver is proposed in this paper. To enable high sensitivity and robust-PVT operation, a fast locking phase-locked-loop (PLL) with initial random phase error reduction is proposed to continuously adjust the center frequency deviations of the SR oscillator (SRO) without interrupting the input data stream. Additionally, a concurrent quenching waveform (CQW) technique is devised to improve the SRO sensitivity and its noise performance. The proposed SRO architecture is controlled by two separate biasing branches to extend the sensitivity accumulation (SA) phase and reduce its noise during the SR phase, compared to the conventional optimal quenching waveform (OQW). The proposed SR receiver is implemented at 2.46 GHz center frequency in 180 nm SMIC CMOS technology and achieves better sensitivity, power consumption, noise performance, and PVT immunity compared with existent SR receiver architectures.

Noise performance of 90 nm CMOS technology

2004 ◽  
Author(s):  
D. Becher ◽  
G. Banerjee ◽  
R. Basco ◽  
C. Hung ◽  
K. Kuhn ◽  
...  
Keyword(s):  
Cmos Technology ◽  
Noise Performance
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