Limits of low noise performance of detector readout front ends in CMOS technology

1990 ◽  
Vol 37 (11) ◽  
pp. 1375-1382 ◽  
Author(s):  
W.M.C. Sansen ◽  
Z.Y. Chang
2015 ◽  
Vol 25 (03) ◽  
pp. 1640019 ◽  
Author(s):  
Daniel Arbet ◽  
Gabriel Nagy ◽  
Martin Kováč ◽  
Viera Stopjaková

In this paper, a fully differential difference amplifier (FDDA) designed in 0.35[Formula: see text][Formula: see text]m CMOS technology is presented. The proposed amplifier reaches high dynamic range (DR) and low input referred noise. Comparison of noise performance of the proposed FDDA to an ordinary differential amplifier has been performed. Achieved results prove that the developed amplifier circuit can be advantageously used in applications that require a fully differential signal. Then, simulation results have been verified by the measurement of prototyped chips. In our work, the proposed amplifier was experimentally employed in the analog frontend of the readout interface (RI) for a Micro-Electro-Mechanical-Systems (MEMS) capacitive microphone.


Electronics ◽  
2019 ◽  
Vol 8 (10) ◽  
pp. 1119 ◽  
Author(s):  
Yin ◽  
Fu ◽  
El-Sankary

A process-voltage-temperature (PVT)-robust, low power, low noise, and high sensitivity, super-regenerative (SR) receiver is proposed in this paper. To enable high sensitivity and robust-PVT operation, a fast locking phase-locked-loop (PLL) with initial random phase error reduction is proposed to continuously adjust the center frequency deviations of the SR oscillator (SRO) without interrupting the input data stream. Additionally, a concurrent quenching waveform (CQW) technique is devised to improve the SRO sensitivity and its noise performance. The proposed SRO architecture is controlled by two separate biasing branches to extend the sensitivity accumulation (SA) phase and reduce its noise during the SR phase, compared to the conventional optimal quenching waveform (OQW). The proposed SR receiver is implemented at 2.46 GHz center frequency in 180 nm SMIC CMOS technology and achieves better sensitivity, power consumption, noise performance, and PVT immunity compared with existent SR receiver architectures.


2017 ◽  
Vol 12 (1) ◽  
pp. 7-17
Author(s):  
André F. Ponchet ◽  
Jacobus W. Swart ◽  
Ezio M. Bastida ◽  
Célio A. Finardi ◽  
Roberto R. Panepucci ◽  
...  

This article presents a complete design flow of a low noise transimpedance amplifier for 10 Gbps optoelectronic receivers. The proposed topology is based on the shunt-shunt structure with negative feedback. A set of equations was deduced from the frequency analysis and noise analysis. An optimization algorithm is proposed in order to maximize the bandwidth and improve the noise performance simultaneously. Experimental results shown a 51 dBΩ transimpedance gain, a 10.54 Ghz bandwidth and an input referred current noise equal to 6.8, the lowest one between other state-of-art designs. The circuit was manufactured in 130 nm RF CMOS technology.


Sensors ◽  
2021 ◽  
Vol 21 (4) ◽  
pp. 1550
Author(s):  
Dominic Greiffenberg ◽  
Marie Andrä ◽  
Rebecca Barten ◽  
Anna Bergamaschi ◽  
Martin Brückner ◽  
...  

Chromium compensated GaAs or GaAs:Cr sensors provided by the Tomsk State University (Russia) were characterized using the low noise, charge integrating readout chip JUNGFRAU with a pixel pitch of 75 × 75 µm2 regarding its application as an X-ray detector at synchrotrons sources or FELs. Sensor properties such as dark current, resistivity, noise performance, spectral resolution capability and charge transport properties were measured and compared with results from a previous batch of GaAs:Cr sensors which were produced from wafers obtained from a different supplier. The properties of the sample from the later batch of sensors from 2017 show a resistivity of 1.69 × 109 Ω/cm, which is 47% higher compared to the previous batch from 2016. Moreover, its noise performance is 14% lower with a value of (101.65 ± 0.04) e− ENC and the resolution of a monochromatic 60 keV photo peak is significantly improved by 38% to a FWHM of 4.3%. Likely, this is due to improvements in charge collection, lower noise, and more homogeneous effective pixel size. In a previous work, a hole lifetime of 1.4 ns for GaAs:Cr sensors was determined for the sensors of the 2016 sensor batch, explaining the so-called “crater effect” which describes the occurrence of negative signals in the pixels around a pixel with a photon hit due to the missing hole contribution to the overall signal causing an incomplete signal induction. In this publication, the “crater effect” is further elaborated by measuring GaAs:Cr sensors using the sensors from 2017. The hole lifetime of these sensors was 2.5 ns. A focused photon beam was used to illuminate well defined positions along the pixels in order to corroborate the findings from the previous work and to further characterize the consequences of the “crater effect” on the detector operation.


2017 ◽  
Vol 26 (05) ◽  
pp. 1750075 ◽  
Author(s):  
Najam Muhammad Amin ◽  
Lianfeng Shen ◽  
Zhi-Gong Wang ◽  
Muhammad Ovais Akhter ◽  
Muhammad Tariq Afridi

This paper presents the design of a 60[Formula: see text]GHz-band LNA intended for the 63.72–65.88[Formula: see text]GHz frequency range (channel-4 of the 60[Formula: see text]GHz band). The LNA is designed in a 65-nm CMOS technology and the design methodology is based on a constant-current-density biasing scheme. Prior to designing the LNA, a detailed investigation into the transistor and passives performances at millimeter-wave (MMW) frequencies is carried out. It is shown that biasing the transistors for an optimum noise figure performance does not degrade their power gain significantly. Furthermore, three potential inductive transmission line candidates, based on coplanar waveguide (CPW) and microstrip line (MSL) structures, have been considered to realize the MMW interconnects. Electromagnetic (EM) simulations have been performed to design and compare the performances of these inductive lines. It is shown that the inductive quality factor of a CPW-based inductive transmission line ([Formula: see text] is more than 3.4 times higher than its MSL counterpart @ 65[Formula: see text]GHz. A CPW structure, with an optimized ground-equalizing metal strip density to achieve the highest inductive quality factor, is therefore a preferred choice for the design of MMW interconnects, compared to an MSL. The LNA achieves a measured forward gain of [Formula: see text][Formula: see text]dB with good input and output impedance matching of better than [Formula: see text][Formula: see text]dB in the desired frequency range. Covering a chip area of 1256[Formula: see text][Formula: see text]m[Formula: see text]m including the pads, the LNA dissipates a power of only 16.2[Formula: see text]mW.


2013 ◽  
Vol 6 (2) ◽  
pp. 109-113 ◽  
Author(s):  
Andrea Malignaggi ◽  
Amin Hamidian ◽  
Georg Boeck

The present paper presents a fully differential 60 GHz four stages low-noise amplifier for wireless applications. The amplifier has been optimized for low-noise, high-gain, and low-power consumption, and implemented in a 90 nm low-power CMOS technology. Matching and common-mode rejection networks have been realized using shielded coplanar transmission lines. The amplifier achieves a peak small-signal gain of 21.3 dB and an average noise figure of 5.4 dB along with power consumption of 30 mW and occupying only 0.38 mm2pads included. The detailed design procedure and the achieved measurement results are presented in this work.


2021 ◽  
Author(s):  
Matthew Al Disi ◽  
Alireza Mohammad Zaki ◽  
Qinwen Fan ◽  
Stoyan Nihtianov

2018 ◽  
Vol 7 (3.6) ◽  
pp. 84
Author(s):  
N Malika Begum ◽  
W Yasmeen

This paper presents an Ultra-Wideband (UWB) 3-5 GHz Low Noise Amplifier (LNA) employing Chebyshev filter. The LNA has been designed using Cadence 0.18um CMOS technology. Proposed LNA achieves a minimum noise figure of 2.2dB, power gain of 9dB.The power consumption is 6.3mW from 1.8V power supply.  


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