An active current-sensing constant-frequency HCC buck converter using phase-frequency-locked techniques

Author(s):  
Jiann-Jong Chen
2021 ◽  
Vol 36 (3) ◽  
pp. 3126-3134
Author(s):  
Jiann-Jong Chen ◽  
Yuh-Shyan Hwang ◽  
Yitsen Ku ◽  
Yun-Hua Li ◽  
Jian-An Chen

2013 ◽  
Vol 2013 (1) ◽  
pp. 000776-000781
Author(s):  
Evan Reutzel ◽  
Rengang Chen ◽  
Scott Ragona ◽  
David Jauregui

A lossless current sensing technique is proposed, which takes advantage of the on-resistance of the sync FET used in the buck converter to sense the current flowing through the device and to reconstruct an emulated version of the inductor current. The current sensing circuit is integrated into the MOSFET driver and co-packaged with a set of FETs in a stacked die arrangement with common lead-frame shared between driver and sync FET to enable accuracy equivalent to or better than DCR sensing. In addition to steady-state operation, modern multiphase controllers are required to drive the buck converter in other operating modes including: Diode Emulation Mode (DEM), body-braking, tri-state (phase off). These additional modes are also correctly emulated by the current sense logic.


2021 ◽  
Vol 11 (6) ◽  
pp. 7922-7926
Author(s):  
D. Bakria ◽  
M. Azzouzi ◽  
D. Gozim

The voltage controlled buck converter by constant-frequency pulse-width modulation in continuous conduction mode gives rise to a variety of nonlinear behaviors depending on the circuit parameters values, which complicate their analysis and control. In this paper, a description of the DC/DC buck converter and an overview of some of its chaotic dynamics is presented. A solution based on the optimized PID controller is suggested to eliminate the observed nonlinear phenomena and to enhance the dynamics of the converter. The parameters of the controller are optimized with the Spotted Hyena Optimizer (SHO) which uses the sum of the error between the reference voltage and the output voltage as well as the error between the values of the inductor current in every switch opening instant to determine the fitness of each solution. The simulations results in MATLAB proved the efficiency of the proposed solution.


2010 ◽  
Vol 11 (1) ◽  
pp. 24-28 ◽  
Author(s):  
Hai-Feng Jin ◽  
Hua-Lan Piao ◽  
Zhi-Yuan Cui ◽  
Nam-Soo Kim

Energies ◽  
2021 ◽  
Vol 14 (18) ◽  
pp. 5911
Author(s):  
Hsiao-Hsing Chou ◽  
Hsin-Liang Chen

This paper presents a buck converter with a novel constant frequency controlled technique, which employs the proposed frequency detector and adaptive on-time control (AOT) logic to lock the switching frequency. The control scheme, design concept, and circuit realization are presented. In contrast to a complex phase lock loop (PLL), the proposed scheme is easy to implement. With this novel technique, a buck converter is designed to produce an output voltage of 1.0–2.5 V at the input voltage of 3.0–3.6 V and the maximum load current of 500 mA. The proposed scheme was verified using SIMPLIS and MathCAD. The simulation results show that the switching frequency variation is less than 1% at an output voltage of 1.0–2.5 V. Furthermore, the recovery time is less than 2 μs for a step-up and step-down load transient. The circuit will be fabricated using UMC 0.18 μm 1P6M CMOS processes. The control scheme, design concept and circuit realization are presented in this paper.


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