scholarly journals Design Flow for Flip-Flop Grouping in Data-Driven Clock Gating

2014 ◽  
Vol 22 (4) ◽  
pp. 771-778 ◽  
Author(s):  
Shmuel Wimer ◽  
Israel Koren
Keyword(s):  
Design Flow ◽  
Data Driven ◽  
Clock Gating ◽  
Flip Flop

Low power aware pulse triggered flip flops using modified clock gating approaches

2018 ◽  
Vol 15 (6) ◽  
pp. 792-803
Author(s):  
Sudhakar Jyothula
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Average Power ◽  
Essential Element ◽  
Battery Life ◽  
Portable Devices ◽  
Clock Gating ◽  
Flip Flop ◽  
Content Type ◽  
Low Leakage

PurposeThe purpose of this paper is to design a low power clock gating technique using Galeor approach by assimilated with replica path pulse triggered flip flop (RP-PTFF).Design/methodology/approachIn the present scenario, the inclination of battery for portable devices has been increasing tremendously. Therefore, battery life has become an essential element for portable devices. To increase the battery life of portable devices such as communication devices, these have to be made with low power requirements. Hence, power consumption is one of the main issues in CMOS design. To reap a low-power battery with optimum delay constraints, a new methodology is proposed by using the advantages of a low leakage GALEOR approach. By integrating the proposed GALEOR technique with conventional PTFFs, a reduction in power consumption is achieved.FindingsThe design was implemented in mentor graphics EDA tools with 130 nm technology, and the proposed technique is compared with existing conventional PTFFs in terms of power consumption. The average power consumed by the proposed technique (RP-PTFF clock gating with the GALEOR technique) is reduced to 47 per cent compared to conventional PTFF for 100 per cent switching activity.Originality/valueThe study demonstrates that RP-PTFF with clock gating using the GALEOR approach is a design that is superior to the conventional PTFFs.

scholarly journals Double Edge-Triggered Half-Static Clock-Gating D-Type Flip-Flop

2021 ◽  
Vol 3 ◽  
pp. 1-4
Author(s):  
Wing-Kong Ng ◽  
Wing-Shan Tam ◽  
Chi-Wah Kok
Keyword(s):  
Clock Gating ◽  
Flip Flop ◽  
Double Edge

scholarly journals Architectural Design of Effective Edge Preserving Median Filter with Error Correction System

2019 ◽  
Vol 8 (2S11) ◽  
pp. 4057-4067
Keyword(s):  
Architectural Design ◽  
Median Filter ◽  
Soft Error ◽  
Data Driven ◽  
Switching Loss ◽  
Clock Gating ◽  
Edge Preservation ◽  
Memory State ◽  
Edge Preserving ◽  
Modular Redundancy

Designing of Median filter that can process 36 pixels at a time with edge preservation similar to a filter of size 9. Median sorting is done using Modified minimum exchange sorting method which attracts double the amount of inputs in order to reduce number of comparators used for median filtering. For the same reason i.e. double the amount of inputs switching loss is high in the circuit therefore data driven clock gating (DDCG) is applied for SRAM to form data driven FIFO. Considering space radiation that could excite memory state, Addition of DMR (Double Modular Redundancy) in FPIC would rectify the soft error that could possibly occur due to radiation in space. Therefore proposed method is capable of producing sharp image, controlling switching loss, minimizes area, and reduces soft errors.

scholarly journals Modelling and Automated Implementation of Optimal Power Saving Strategies in Coarse-Grained Reconfigurable Architectures

2016 ◽  
Vol 2016 ◽  
pp. 1-27 ◽  
Author(s):  
Francesca Palumbo ◽  
Tiziana Fanni ◽  
Carlo Sau ◽  
Paolo Meloni ◽  
Luigi Raffo
Keyword(s):  
Power Saving ◽  
Design Flow ◽  
Coarse Grained ◽  
Management Support ◽  
Clock Gating ◽  
Baseline Design ◽  
Heterogeneous Architectures ◽  
Optimal Power ◽  
Implementation Costs ◽  
Optimal Implementation

This paper focuses on how to efficiently reduce power consumption in coarse-grained reconfigurable designs, to allow their effective adoption in heterogeneous architectures supporting and accelerating complex and highly variable multifunctional applications. We propose a design flow for this kind of architectures that, besides their automatic customization, is also capable of determining their optimal power management support. Power and clock gating implementation costs are estimated in advance, before their physical implementation, on the basis of the functional, technological, and architectural parameters of the baseline design. Experimental results, on 90 and 45 nm CMOS technologies, demonstrate that the proposed approach guides the designer towards optimal implementation.

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