Adaptive Bus Encoding for Transition Reduction on Off-Chip Buses With Dynamically Varying Switching Characteristics

2017 ◽  
Vol 25 (11) ◽  
pp. 3057-3066 ◽  
Author(s):  
Sumantra Sarkar ◽  
Ayan Biswas ◽  
Anindya Sundar Dhar ◽  
Rahul M. Rao
2012 ◽  
Vol 27 (3) ◽  
pp. 323-326
Author(s):  
Zhen-Guo JI ◽  
Jun-Jie WANG ◽  
Qi-Nan MAO ◽  
Jun-Hua XI

2020 ◽  
Vol 12 (1) ◽  
pp. 01007-1-01007-6
Author(s):  
Chandra Prakash Gupta ◽  
◽  
Praveen K. Jain ◽  
Umesh Chand ◽  
Shashi Kant Sharma ◽  
...  

2019 ◽  
Vol 9 (4) ◽  
pp. 486-493 ◽  
Author(s):  
S. Sahoo ◽  
P. Manoravi ◽  
S.R.S. Prabaharan

Introduction: Intrinsic resistive switching properties of Pt/TiO2-x/TiO2/Pt crossbar memory array has been examined using the crossbar (4×4) arrays fabricated by using DC/RF sputtering under specific conditions at room temperature. Materials and Methods: The growth of filament is envisaged from bottom electrode (BE) towards the top electrode (TE) by forming conducting nano-filaments across TiO2/TiO2-x bilayer stack. Non-linear pinched hysteresis curve (a signature of memristor) is evident from I-V plot measured using Pt/TiO2-x /TiO2/Pt bilayer device (a single cell amongst the 4×4 array is used). It is found that the observed I-V profile shows two distinguishable regions of switching symmetrically in both SET and RESET cycle. Distinguishable potential profiles are evident from I-V curve; in which region-1 relates to the electroformation prior to switching and region-2 shows the switching to ON state (LRS). It is observed that upon reversing the polarity, bipolar switching (set and reset) is evident from the facile symmetric pinched hysteresis profile. Obtaining such a facile switching is attributed to the desired composition of Titania layers i.e. the rutile TiO2 (stoichiometric) as the first layer obtained via controlled post annealing (650oC/1h) process onto which TiO2-x (anatase) is formed (350oC/1h). Results: These controlled processes adapted during the fabrication step help manipulate the desired potential barrier between metal (Pt) and TiO2 interface. Interestingly, this controlled process variation is found to be crucial for measuring the switching characteristics expected in Titania based memristor. In order to ensure the formation of rutile and anatase phases, XPS, XRD and HRSEM analyses have been carried out. Conclusion: Finally, the reliability of bilayer memristive structure is investigated by monitoring the retention (104 s) and endurance tests which ensured the reproducibility over 10,000 cycles.


2021 ◽  
Vol 11 (15) ◽  
pp. 7057
Author(s):  
Lin Wang ◽  
Zhe Cheng ◽  
Zhi-Guo Yu ◽  
De-Feng Lin ◽  
Zhe Liu ◽  
...  

Half-bridge modules with integrated GaN high electron mobility transistors (HEMTs) and driver dies were designed and fabricated in this research. Our design uses flip-chip technology for fabrication, instead of more generally applied wire bonding, to reduce parasitic inductance in both the driver-gate and drain-source loops. Modules were prepared using both methods and the double-pulse test was applied to evaluate and compare their switching characteristics. The gate voltage (Vgs) waveform of the flip-chip module showed no overshoot during the turn-on period, and a small oscillation during the turn-off period. The probabilities of gate damage and false turn-on were greatly reduced. The inductance in the drain-source loop of the module was measured to be 3.4 nH. The rise and fall times of the drain voltage (Vds) were 12.9 and 5.8 ns, respectively, with an overshoot of only 4.8 V during the turn-off period under Vdc = 100 V. These results indicate that the use of flip-chip technology along with the integration of GaN HEMTs with driver dies can effectively reduce the parasitic inductance and improve the switching performance of GaN half-bridge modules compared to wire bonding.


2021 ◽  
Vol 11 (1) ◽  
Author(s):  
Sera Kwon ◽  
Min-Jung Kim ◽  
Kwun-Bum Chung

AbstractTiOx-based resistive switching devices have recently attracted attention as a promising candidate for next-generation non-volatile memory devices. A number of studies have attempted to increase the structural density of resistive switching devices. The fabrication of a multi-level switching device is a feasible method for increasing the density of the memory cell. Herein, we attempt to obtain a non-volatile multi-level switching memory device that is highly transparent by embedding SiO2 nanoparticles (NPs) into the TiOx matrix (TiOx@SiO2 NPs). The fully transparent resistive switching device is fabricated with an ITO/TiOx@SiO2 NPs/ITO structure on glass substrate, and it shows transmittance over 95% in the visible range. The TiOx@SiO2 NPs device shows outstanding switching characteristics, such as a high on/off ratio, long retention time, good endurance, and distinguishable multi-level switching. To understand multi-level switching characteristics by adjusting the set voltages, we analyze the switching mechanism in each resistive state. This method represents a promising approach for high-performance non-volatile multi-level memory applications.


2013 ◽  
Vol 63 (11) ◽  
pp. 2269-2272 ◽  
Author(s):  
Seoung-Hwan Park ◽  
Woo-Pyo Hong ◽  
Jong-Jae Kim

Materials ◽  
2021 ◽  
Vol 14 (13) ◽  
pp. 3554
Author(s):  
Jaeyeop Na ◽  
Jinhee Cheon ◽  
Kwangsoo Kim

In this paper, a novel 4H-SiC split heterojunction gate double trench metal-oxide-semiconductor field-effect transistor (SHG-DTMOS) is proposed to improve switching speed and loss. The device modifies the split gate double trench MOSFET (SG-DTMOS) by changing the N+ polysilicon split gate to the P+ polysilicon split gate. It has two separate P+ shielding regions under the gate to use the P+ split polysilicon gate as a heterojunction body diode and prevent reverse leakage `current. The static and most dynamic characteristics of the SHG-DTMOS are almost like those of the SG-DTMOS. However, the reverse recovery charge is improved by 65.83% and 73.45%, and the switching loss is improved by 54.84% and 44.98%, respectively, compared with the conventional double trench MOSFET (Con-DTMOS) and SG-DTMOS owing to the heterojunction.


Author(s):  
Valery Barmin ◽  
Pavel Priputnev ◽  
Vladimir Konev ◽  
Sergei Maltsev ◽  
Ilya Romanchenko ◽  
...  

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