Power Efficient Sense Amplifier For Emerging Non Volatile Memories

2020 ◽  
Author(s):  
Vivek Tyagi ◽  
Vikas Rana ◽  
Laura Capecchi ◽  
Marcella Carissimi ◽  
Marco Pasotti
Keyword(s):  
Power Efficient ◽  
Sense Amplifier

Power-Efficient Fast Write and Hidden Refresh of ReRAM Using an ADC-Based Sense Amplifier

2013 ◽  
Vol 60 (11) ◽  
pp. 776-780 ◽  
Author(s):  
Sang-Yun Kim ◽  
Jong-Min Baek ◽  
Dong-Jin Seo ◽  
Jae-Koo Park ◽  
Jung-Hoon Chun ◽  
...  
Keyword(s):  
Power Efficient ◽  
Sense Amplifier

LOW POWER AND HIGH PERFORMANCE SINGLE-ENDED SENSE AMPLIFIER

2013 ◽  
Vol 22 (07) ◽  
pp. 1350062 ◽  
Author(s):  
AJAY KUMAR SINGH ◽  
MAH MENG SEONG ◽  
C. M. R. PRABHU
Keyword(s):  
Power Consumption ◽  
High Performance ◽  
Voltage Drop ◽  
Cmos Technology ◽  
Power Efficient ◽  
Sense Amplifier ◽  
Current Voltage ◽  
Direct Current Voltage ◽  
Voltage Conversion ◽  
Lower Voltage

This paper presents a new power efficient single ended sense amplifier (SA). The proposed circuit is based on the direct current voltage conversion technique. It has been simulated using Microwind3 and DSCH3 tools (advanced BSIM 4 level) for 90 nm CMOS technology in terms of power consumption, sense time and results were compared to other circuits. The proposed SA circuit consumes more than 50% less power and gives 90% faster sensing speed compared to other circuits. The lower power consumption is due to lower leakage current, lower voltage drop on bit-line and faster speed is due to positive feedback of the circuit. The proposed circuit is more robust against any process and temperature variation.

AN ULTRA LOW-POWER CURRENT-MODE SENSE AMPLIFIER FOR SRAM APPLICATIONS

2005 ◽  
Vol 14 (05) ◽  
pp. 939-951 ◽  
Author(s):  
ZHI-HUI KONG ◽  
KIAT-SENG YEO ◽  
CHIP-HONG CHANG
Keyword(s):  
Low Power ◽  
Low Voltage ◽  
Current Mode ◽  
Cmos Technology ◽  
Ultra Low Power ◽  
Power Efficient ◽  
Power Characteristics ◽  
Sense Amplifier ◽  
Micro Power ◽  
Power Delay Product

A novel micro-power current sense amplifier employing a cross-coupled current-mirror configuration is presented. The circuit is designed for low-voltage low-power SRAM applications. Its sensing speed is independent of the bit-line capacitances and is almost insensitive to the data-line capacitances. Extensive post-layout simulation results based on a 1.8 V/0.18 μm CMOS technology from Chartered Semiconductor Manufacturing Ltd. (CHRT) have verified that the new sense amplifier promises a much sought-after power-efficient advantage and a note-worthy power-delay product superiority over the conventional and recently reported sense amplifier circuits. These attributes of the proposed sense amplifier make it judiciously appropriate for use in the contemporary high-complexity regime, which incessantly craves for low-power characteristics.

scholarly journals Power-Efficient Explicit-Pulsed Dual-Edge Triggered Sense-Amplifier Flip-Flops

2011 ◽  
Vol 19 (1) ◽  
pp. 1-9 ◽  
Author(s):  
Myint Wai Phyu ◽  
Kangkang Fu ◽  
Wang Ling Goh ◽  
Kiat-Seng Yeo
Keyword(s):  
Power Efficient ◽  
Sense Amplifier
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