Mitigating the Impact of Component Variations on Narrow-Band Low Noise Amplifiers for System-on-Chip Applications

2006 ◽  
Author(s):  
Arthur Nieuwoudt ◽  
Tamer Ragheb ◽  
Yehia Massoud
Keyword(s):  
Narrow Band ◽  
Low Noise ◽  
System On Chip ◽  
Low Noise Amplifiers ◽  
On Chip ◽  
The Impact

ON-CHIP INDUCTORS OPTIMIZATION FOR ULTRA WIDE BAND LOW NOISE AMPLIFIERS

2011 ◽  
Vol 20 (07) ◽  
pp. 1231-1242 ◽  
Author(s):  
J. DEL PINO ◽  
SUNIL L. KHEMCHANDANI ◽  
ROBERTO DÍAZ-ORTEGA ◽  
R. PULIDO ◽  
H. GARCÍA-VÁZQUEZ
Keyword(s):  
Quality Factor ◽  
Noise Figure ◽  
Impedance Matching ◽  
Broad Band ◽  
Wide Band ◽  
Design Guidelines ◽  
Low Noise ◽  
Low Noise Amplifiers ◽  
Integrated Inductor ◽  
On Chip

In this work, the influence of the inductor quality factor in wide band low noise amplifiers has been studied. Electromagnetic simulations have been used to model the integrated inductor broad band response. The influence of the quality factor on LNA performance of the inductors that compound the impedance matching networks, inductive degeneration and broadband load has been studied, obtaining design guidelines for optimizing the amplifier gain flatness. Using this guidelines, an LNA with wideband input matching, shunt-peaking load, and an output buffer was designed. Using Austria Mikro Systems BiCMOS 0.35 m process, a prototype has been fabricated achieving the following measured specifications: maximum gain of 12.5 dB at 3.4 GHz with a -3 dB bandwidth of 1.7–5.3 GHz, noise figure from 4.3 to 5.2 dB, and unity gain at 9.4 GHz.

scholarly journals Measuring Static Parameters of Embedded ADC Core

2011 ◽  
Vol 62 (2) ◽  
pp. 80-86
Author(s):  
Franc Novak ◽  
Peter Mrak ◽  
Anton Biasizzo
Keyword(s):  
Feasibility Study ◽  
Theoretical Background ◽  
System On Chip ◽  
Test Time ◽  
Hardware Overhead ◽  
Self Test ◽  
Built In Self Test ◽  
On Chip ◽  
The Impact ◽  
Minimal Hardware

Measuring Static Parameters of Embedded ADC CoreThe paper presents the results of a feasibility study of measuring static parameters of ADC cores embedded in a System-on-Chip. Histogram based technique is employed because it is suitable for built-in self-test. While the theoretical background of the technique has been covered by numerous papers, less attention has been given to implementations in practice. Our goal was the implementation of histogram test in a IEEE Std 1500 wrapper. Two different solutions pursuing either minimal test time or minimal hardware overhead are described. The impact of MOS switches at ADC input on the performed measurements was considered.

scholarly journals A New Fractal-Based Design of Stacked Integrated Transformers

2008 ◽  
Vol 2008 ◽  
pp. 1-8 ◽  
Author(s):  
Goran Stojanović ◽  
Milan Radovanović ◽  
Vasa Radonić
Keyword(s):  
Integrated Circuits ◽  
Mobile Communications ◽  
Wide Band ◽  
Low Noise ◽  
Low Noise Amplifiers ◽  
Radio Frequency Integrated Circuits ◽  
Band Frequency ◽  
Electromagnetic Simulations ◽  
On Chip ◽  
Silicon Based

Silicon-based radio-frequency integrated circuits are becoming more and more competitive in wide-band frequency range. An essential component of these ICs is on-chip (integrated) transformer. It is widely used in mobile communications, microwave integrated circuits, low-noise amplifiers, active mixers, and baluns. This paper deals with the design, simulation, and analysis of novel fractal configurations of the primary and secondary coils of the integrated transformers. Integrated stacked transformers, which use fractal curves (Hilbert, Peano, and von Koch) to form the primary and secondary windings, are presented. In this way, the occupied area on the chip is lower and a number of lithographic processes are decreased. The performances of the proposed integrated transformers are investigated with electromagnetic simulations up to 20 GHz. The influence of the order of fractal curves and the width of conductive lines on the inductance and quality factor is also described.

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