ON-CHIP INDUCTORS OPTIMIZATION FOR ULTRA WIDE BAND LOW NOISE AMPLIFIERS

2011 ◽  
Vol 20 (07) ◽  
pp. 1231-1242 ◽  
Author(s):  
J. DEL PINO ◽  
SUNIL L. KHEMCHANDANI ◽  
ROBERTO DÍAZ-ORTEGA ◽  
R. PULIDO ◽  
H. GARCÍA-VÁZQUEZ
Keyword(s):  
Quality Factor ◽  
Noise Figure ◽  
Impedance Matching ◽  
Broad Band ◽  
Wide Band ◽  
Design Guidelines ◽  
Low Noise ◽  
Low Noise Amplifiers ◽  
Integrated Inductor ◽  
On Chip

In this work, the influence of the inductor quality factor in wide band low noise amplifiers has been studied. Electromagnetic simulations have been used to model the integrated inductor broad band response. The influence of the quality factor on LNA performance of the inductors that compound the impedance matching networks, inductive degeneration and broadband load has been studied, obtaining design guidelines for optimizing the amplifier gain flatness. Using this guidelines, an LNA with wideband input matching, shunt-peaking load, and an output buffer was designed. Using Austria Mikro Systems BiCMOS 0.35 m process, a prototype has been fabricated achieving the following measured specifications: maximum gain of 12.5 dB at 3.4 GHz with a -3 dB bandwidth of 1.7–5.3 GHz, noise figure from 4.3 to 5.2 dB, and unity gain at 9.4 GHz.

Design Analysis of Inductorless Active Loaded Low Power UWB LNA Using Noise Cancellation Technique

Frequenz ◽  
2020 ◽  
Vol 74 (3-4) ◽  
pp. 137-144 ◽  
Author(s):  
Dheeraj Kalra ◽  
Manish Kumar ◽  
Aasheesh Shukla ◽  
Laxman Singh ◽  
Zainul Abdin Jaffery
Keyword(s):  
Low Power ◽  
Noise Figure ◽  
Broad Band ◽  
Wide Band ◽  
Cmos Technology ◽  
Noise Cancellation ◽  
Low Noise ◽  
Design Analysis ◽  
Common Source ◽  
Power Gain

AbstractThis paper includes a design analysis of an inductorless low-power (LP) low-noise amplifier (LNA) with active load for Ultra Wide Band (UWB) applications. The proposed LNA consists of two parallel paths, one is the common source (CS) path and second is the CG path. The CG path has the edge advantage of improving overall Noise figure (NF) due to wide band impedance matching in UWB, while the CS path provides high power gain. A method for noise cancellation is adopted, to reduce the noise of CS path with the help of CG path. The proposed LNA successfully simulated in 90 nm CMOS technology. The results of proposed work indicate optimization at frequency 5.70 GHz with 3 dB bandwidth of 4.3 GHz–8.9 GHz. All simulations have been done for a range of frequency 03 GHz–13 GHz in Cadence virtuoso software. The results quoted 1.15 dB NF, −18.12 dB S11, 13.7 dB S21, maximum operating power gain (GP) 11.756 dB at frequency 5.7 GHz and available power gain (GA) is 10.17 dB at frequency 8.61 GHz, with 0.6 V, 0.92 mW broad band LNA.

scholarly journals Bandwidth Analysis of a Broadband Amplifier with Two-Stage Matching System Using the Smith Chart

2021 ◽  
Vol 24 (3) ◽  
pp. 53-60
Author(s):  
A.A. Sherstneva
Keyword(s):  
Noise Figure ◽  
Impedance Matching ◽  
Low Noise ◽  
Low Noise Amplifiers ◽  
Matching Problem ◽  
Two Stage ◽  
Analysis And Design ◽  
Design Variables ◽  
Stage Matching ◽  
Smith Chart

This paper describes a novel trace structure for the analysis and design of two-stage Broadband Frequency Low Noise Amplifiers based on standard Smith chart procedures and program algorithm realization. The method allows to put the transistor's S-parameters and details of the source and load networks and to interactively explore the effects of these quantities on design variables such as gain, noise figure and stability. It also facilitates the design of two-element matching networks to transform the source and load impedances to optimum values to achieve the desired gain and noise performance. The extended Smith chart concept is proposed to enable the advanced graphical interpretation of devices containing complex properties. This methodology is based on the Smith chart concept, and makes it easy to deal with devices containing signal sources, nonlinearity, very high Q factors and negative resistances. The concept of explaining the use of the Smith chart in combination with using modern tools as MATLAB scripts is exemplified in graphical forms. Phyton-based program contains the algorithm for parameters calculation. It explains the procedure that must be used to solve the two-stage impedance-matching problem. The point of this proposal is using of Smith chart plane for the graphical processing for its application to oscillator analysis. To demonstrate the effective usage of this methodology an interpretation and analysis of the oscillator, especially in terms of gain, noise and stability, are provided. The practical relevance concludes results of multistage design using impedance matching LC networks for the intersection level. The values of the parameters of the integrated microcircuit confirm the possibility of using the calculation methodology considered in the paper. The proposed solution is validated with extensive RF measurements at 3.5 GHz and is benchmarked against several frequency ranges for noise, stability and gain values. The methodology shown in the paper can be used in the development and design of modern microwave amplifiers, as well as for research and analysis of the efficiency of existing devices.

A 1.8 to 4 GHz inductor-less highly linear CMOS LNA for wire-less receivers

2021 ◽  
pp. 11-20
Author(s):  
Nguyen Huu Tho
Keyword(s):  
Noise Figure ◽  
Impedance Matching ◽  
Wide Band ◽  
Low Noise ◽  
Common Source ◽  
Cmos Process ◽  
Wide Range ◽  
Active Feedback ◽  
Cmos Lna ◽  
Noise Amplifier

This paper presents an inductor-less wide-band highly linear low-noise amplifier (LNA) for wire-less receivers. The inductor-less LNA consists of a complementary current-reuse common source amplifier combined with a low-current active feedback to obtain wide range input impedance matching and low noise figure. In our LNA, a degeneration resistor is utilized to improve linearity of the LNA. Furthermore, we designed a bypass mode for the LNA to extend the range of its applications. The proposed LNA is implemented in 28 nm CMOS process. It has a gain of 14.9 dB and a bandwidth of 2.2 GHz. The noise figure (NF) is 1.95 dB and the third-order input intercept point (IIP3) is 24.8 dBm at 2.3 GHz. It consumes 17.2 mW at a 0.9-V supply and has an area of 0.011 mm2.

scholarly journals A New Fractal-Based Design of Stacked Integrated Transformers

2008 ◽  
Vol 2008 ◽  
pp. 1-8 ◽  
Author(s):  
Goran Stojanović ◽  
Milan Radovanović ◽  
Vasa Radonić
Keyword(s):  
Integrated Circuits ◽  
Mobile Communications ◽  
Wide Band ◽  
Low Noise ◽  
Low Noise Amplifiers ◽  
Radio Frequency Integrated Circuits ◽  
Band Frequency ◽  
Electromagnetic Simulations ◽  
On Chip ◽  
Silicon Based

Silicon-based radio-frequency integrated circuits are becoming more and more competitive in wide-band frequency range. An essential component of these ICs is on-chip (integrated) transformer. It is widely used in mobile communications, microwave integrated circuits, low-noise amplifiers, active mixers, and baluns. This paper deals with the design, simulation, and analysis of novel fractal configurations of the primary and secondary coils of the integrated transformers. Integrated stacked transformers, which use fractal curves (Hilbert, Peano, and von Koch) to form the primary and secondary windings, are presented. In this way, the occupied area on the chip is lower and a number of lithographic processes are decreased. The performances of the proposed integrated transformers are investigated with electromagnetic simulations up to 20 GHz. The influence of the order of fractal curves and the width of conductive lines on the inductance and quality factor is also described.

scholarly journals CMOS low noise amplifiers for 1.575 GHz GPS applications

2009 ◽  
Vol 7 ◽  
pp. 145-150 ◽  
Author(s):  
M. Isikhan ◽  
A. Richter
Keyword(s):  
Noise Figure ◽  
Supply Voltage ◽  
Low Noise ◽  
Performance Criteria ◽  
Low Noise Amplifiers ◽  
Cmos Process ◽  
Quality Factors ◽  
Voltage Range ◽  
Noise Amplifier ◽  
On Chip

Abstract. This paper presents Low Noise Amplifier (LNA) versions designed for 1.575 GHz L1 Band Global Positioning System (GPS) applications. A 0.35 μm standard CMOS process is used for implementation of these design versions. Different versions are designed to compare the results, analyze some effects and optimize some critical performance criteria. On-chip inductors with different quality factors and a slight topology change are utilized to achieve this variety. It is proven through both on-wafer and on-PCB measurements that the LNA versions operate at a supply voltage range varying from 2.1 V to 3.6 V drawing a current of 10 mA and achieve a gain of 13 dB to 17 dB with a Noise Figure (NF) of 1.5 dB. Input referred 1 dB compression point (ICP) is measured as −5.5 dBm and −10 dBm for different versions.

60 GHz-Band Low-Noise Amplifier

2017 ◽  
Vol 26 (05) ◽  
pp. 1750075 ◽  
Author(s):  
Najam Muhammad Amin ◽  
Lianfeng Shen ◽  
Zhi-Gong Wang ◽  
Muhammad Ovais Akhter ◽  
Muhammad Tariq Afridi
Keyword(s):  
Transmission Line ◽  
Quality Factor ◽  
Noise Figure ◽  
Cmos Technology ◽  
Low Noise ◽  
Constant Current ◽  
60 Ghz ◽  
Frequency Range ◽  
Constant Current Density ◽  
Chip Area

This paper presents the design of a 60[Formula: see text]GHz-band LNA intended for the 63.72–65.88[Formula: see text]GHz frequency range (channel-4 of the 60[Formula: see text]GHz band). The LNA is designed in a 65-nm CMOS technology and the design methodology is based on a constant-current-density biasing scheme. Prior to designing the LNA, a detailed investigation into the transistor and passives performances at millimeter-wave (MMW) frequencies is carried out. It is shown that biasing the transistors for an optimum noise figure performance does not degrade their power gain significantly. Furthermore, three potential inductive transmission line candidates, based on coplanar waveguide (CPW) and microstrip line (MSL) structures, have been considered to realize the MMW interconnects. Electromagnetic (EM) simulations have been performed to design and compare the performances of these inductive lines. It is shown that the inductive quality factor of a CPW-based inductive transmission line ([Formula: see text] is more than 3.4 times higher than its MSL counterpart @ 65[Formula: see text]GHz. A CPW structure, with an optimized ground-equalizing metal strip density to achieve the highest inductive quality factor, is therefore a preferred choice for the design of MMW interconnects, compared to an MSL. The LNA achieves a measured forward gain of [Formula: see text][Formula: see text]dB with good input and output impedance matching of better than [Formula: see text][Formula: see text]dB in the desired frequency range. Covering a chip area of 1256[Formula: see text][Formula: see text]m[Formula: see text]m including the pads, the LNA dissipates a power of only 16.2[Formula: see text]mW.

Design of 3.1-10.6GHz CMOS LNA Based on Input Matching Technique of Common-Gate Topology

2013 ◽  
Vol 479-480 ◽  
pp. 1014-1017
Author(s):  
Yi Cheng Chang ◽  
Meng Ting Hsu ◽  
Yu Chang Hsieh
Keyword(s):  
Noise Figure ◽  
Supply Voltage ◽  
Average Power ◽  
Wide Band ◽  
Low Noise ◽  
Input Matching ◽  
Common Gate ◽  
Cmos Lna ◽  
Noise Amplifier ◽  
Is Design

In this study, three stage ultra-wide-band CMOS low-noise amplifier (LNA) is presented. The UWB LNA is design in 0.18μm TSMC CMOS technique. The LNA input and output return loss are both less than-10dB, and achieved 10dB of average power gain, the minimum noise figure is 6.55dB, IIP3 is about-9.5dBm. It consumes 11mW from a 1.0-V supply voltage.

scholarly journals CMOS Ultra-Wideband Low Noise Amplifier Design

2013 ◽  
Vol 2013 ◽  
pp. 1-6 ◽  
Author(s):  
K. Yousef ◽  
H. Jia ◽  
R. Pokharel ◽  
A. Allam ◽  
M. Ragab ◽  
...  
Keyword(s):  
Impedance Matching ◽  
Cmos Technology ◽  
Low Noise ◽  
Low Noise Amplifier ◽  
Ultra Wideband ◽  
Output Impedance ◽  
Integrated Inductor ◽  
Technology Process ◽  
Amplifier Design ◽  
Noise Amplifier

This paper presents the design of ultra-wideband low noise amplifier (UWB LNA). The proposed UWB LNA whose bandwidth extends from 2.5 GHz to 16 GHz is designed using a symmetric 3D RF integrated inductor. This UWB LNA has a gain of 11 ± 1.0 dB and a NF less than 3.3 dB. Good input and output impedance matching and good isolation are achieved over the operating frequency band. The proposed UWB LNA is driven from a 1.8 V supply. The UWB LNA is designed and simulated in standard TSMC 0.18 µm CMOS technology process.

scholarly journals Design of Low Power UWB CMOS Low Noise Amplifier using Active Inductor for WLAN Receiver

2018 ◽  
Vol 7 (2.24) ◽  
pp. 448
Author(s):  
S Manjula ◽  
M Malleshwari ◽  
M Suganthy
Keyword(s):  
Low Power ◽  
Noise Figure ◽  
Wide Band ◽  
Cmos Technology ◽  
Low Noise ◽  
Low Noise Amplifier ◽  
Design System ◽  
Active Inductor ◽  
Chip Area ◽  
Noise Amplifier

This paper presents a low power Low Noise Amplifier (LNA) using 0.18µm CMOS technology for ultra wide band (UWB) applications. gm boosting common gate (CG) LNA is designed to improve the noise performance.  For the reduction of on chip area, active inductor is employed at the input side of the designed LNA for input impedance matching. The proposed UWB LNA is designed using Advanced Design System (ADS) at UWB frequency of 3.1-10.6 GHz. Simulation results show that the gain of 10.74+ 0.01 dB, noise figure is 4.855 dB, input return loss <-13 dB and 12.5 mW power consumption.  

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