Optimized SRAM cell design for high speed and low power applications

2011 World Congress on Information and Communication Technologies ◽

10.1109/wict.2011.6141446 ◽

2011 ◽

Author(s):

Anand Kumar ◽

Shalini ◽

Imran Ahmed Khan

Keyword(s):

Low Power ◽

Cell Design ◽

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Robust Low Power 12T SRAM Cell Design based Full Adder using 120nm,90nm,65nm and 45nm Technologies

International Journal for Research in Applied Science and Engineering Technology ◽

10.22214/ijraset.2018.4060 ◽

2018 ◽

Vol 6 (4) ◽

pp. 332-340

Author(s):

Syed Mohammad Imran Ali

Keyword(s):

Low Power ◽

Cell Design ◽

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Low power SRAM cell design for FinFET and CNTFET technologies

International Conference on Green Computing ◽

10.1109/greencomp.2010.5598266 ◽

2010 ◽

Author(s):

Jose G. Delgado-Frias ◽

Zhe Zhang ◽

Michael A. Turi

Keyword(s):

Low Power ◽

Cell Design ◽

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An ultra-low-power and high-performance SRAM cell design based on GNRFETs

International Journal of Electronics Letters ◽

10.1080/21681724.2020.1794048 ◽

2020 ◽

pp. 1-11

Author(s):

Pramod Kumar Patel ◽

Manzar Malik ◽

Tarun Kumar Gupta

Keyword(s):

Low Power ◽

High Performance ◽

Cell Design ◽

Ultra Low Power ◽

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High-speed reduced-leakage SRAM memory cell design techniques for low-power 65nm FD-SOI/SON CMOS technology

Microelectronics Journal ◽

10.1016/j.mejo.2014.04.032 ◽

2014 ◽

Vol 45 (7) ◽

pp. 848-856 ◽

Author(s):

Deepon Saha ◽

Subir Kumar Sarkar

Keyword(s):

Low Power ◽

Memory Cell ◽

Cmos Technology ◽

Cell Design ◽

Sram Memory ◽

Design Techniques

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Design of Novel SRAM cell using Hybrid VLSI Techniques for Low Power and High Speed in Embedded Memories

2018 International Conference on Intelligent Computing and Communication for Smart World (I2C2SW) ◽

10.1109/i2c2sw45816.2018.8997525 ◽

2018 ◽

Author(s):

K. Gavaskar ◽

U.S. Ragupathy ◽

D. Malathi ◽

G. Ravivarma

Keyword(s):

Low Power ◽

Sram Cell ◽

Embedded Memories

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Design of an AAM 6T-SRAM Cell Variation in the Supply Voltage for Low Power Dissipation and High Speed Applications using 20nm Finfet Technology

2020 International Conference on Inventive Computation Technologies (ICICT) ◽

10.1109/icict48043.2020.9112590 ◽

2020 ◽

Author(s):

Bharatha Satheesh ◽

Prabhu Benakop

Keyword(s):

Low Power ◽

Power Dissipation ◽

Supply Voltage ◽

Sram Cell ◽

Low Power Dissipation ◽

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A current-sensed high-speed and low-power first-in-first-out memory using a wordline/bitline-swapped dual-port SRAM cell

IEEE Journal of Solid-State Circuits ◽

10.1109/jssc.2002.1004578 ◽

2002 ◽

Vol 37 (6) ◽

pp. 735-750 ◽

Author(s):

N. Shibata ◽

M. Watanabe ◽

Y. Tanabe

Keyword(s):

Low Power ◽

Sram Cell ◽

First In First Out ◽

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CNTFET modeling and low power SRAM cell design

2016 IEEE 5th Global Conference on Consumer Electronics ◽

10.1109/gcce.2016.7800437 ◽

2016 ◽

Author(s):

Amandeep Singh ◽

Mamta Khosla ◽

Balwinder Raj

Keyword(s):

Low Power ◽

Cell Design ◽

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Ultra-Low Power Sub-threshold SRAM Cell Design to Improve Read Static Noise Margin

Progress in VLSI Design and Test - Lecture Notes in Computer Science ◽

10.1007/978-3-642-31494-0_16 ◽

2012 ◽

pp. 139-146 ◽

Author(s):

Chandrabhan Kushwah ◽

Santosh K. Vishvakarma

Keyword(s):

Low Power ◽

Cell Design ◽

Static Noise Margin ◽

Ultra Low Power ◽

Noise Margin ◽

Sram Cell ◽

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A Novel SRAM Cell Design with a Body-Bias Controller Circuit for Low Leakage, High Speed and Improved Stability

Wireless Personal Communications ◽

10.1007/s11277-016-3788-5 ◽

2016 ◽

Vol 94 (4) ◽

pp. 3513-3529 ◽

Author(s):

Rohit Lorenzo ◽

Saurabh Chaudhury

Keyword(s):

Cell Design ◽

Low Leakage ◽

Sram Cell ◽

Improved Stability ◽

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