A Technique for Embedding SPICE in a Simulink Environment for MEMS Simulations

Author(s):  
Christopher G. Wilson ◽  
Robert Dean ◽  
George T. Flowers ◽  
John Y. Hung

Computer simulations are powerful tools in the designer’s toolbox, giving an estimate of what the device will actually do once realized. Two such tools, Simulink and SPICE are commonly used to design, simulate, and verify models in the mechanical and electronic domains, respectively. Challenges can arise, however, when attempting to simulate behaviors of hybrid systems that possies both electronic and mechancial subsystems. For example, in microelectromechanical systems (MEMS) designs, variable capacitors are frequent methods for sensing and actuating. While straightforward to model in Simulink, MEMS are not intuitive to model in SPICE, where the control electronics are simulated. On the other hand, SIMULINK is a less mature tool than SPICE for simulating electronic behaviors — SPICE already posseses large libraries of electronic device models. Thus, current MEMS designers lack a straightforward method to simulate and verify variable capacitors in a transient electronic circuit in SPICE, since the entire mechanical system must be converted from Simulink and verified. This paper presents a technique for embedding NGSPICE, an open-source SPICE implementation, inside a Simulink model via a S-function block, enabling a full system model for transient responses to be realized. A Level 2 M-file S-function block implements the calling and parsing of the associated electronic subsystem circuit file. The required modifications for the circuit file to the Simulink model are described. Validation testing using a low-pass filter type circuits with constant and variable capacitance are presented. Some examples are presented and discussed.

1978 ◽  
Vol AES-14 (2) ◽  
pp. 393-400
Author(s):  
Toshihiko Yamawaki ◽  
Taikyu Kim

2018 ◽  
pp. 6-12 ◽  
Author(s):  
R. V. Magerramov

This article describes the method of converting an analog signal into a digital code using a phase locked loop (PLL) circuit. The functional structure of the voltage-to-digital conversion circuit is considered. The application of the principle of phase-locked loop for controlling the duty cycle of the output signal of a phase detector when the voltage at the positive input of the operational amplifier included in the low-pass filter is investigated. In the modern world, analog-to-digital converters (ADCs) are available in almost every electronic device. The application of different ADC architectures is determined by their parameters and features by circuit and technological implementation. The phase-locked loop with a digital part (16-bit counter, storage register and data transfer interface) allows to obtain a precision analog-to-digital converter, based on a relatively simple circuit design, which has high accuracy and low noise level. Negative feedback of the PLL loop makes it possible to level the error of the passive elements of the low-pass filter (LPF) and the voltage controlled oscillator (VCO). The result of this work is an analysis of the ADC characteristics in the technological basis of 250 nm.


2014 ◽  
Vol 1049-1050 ◽  
pp. 605-608
Author(s):  
Chun Yu Wang ◽  
Hai Bo Yu ◽  
Ying Hui Xu ◽  
Min Lei ◽  
Jia Liu

Metering chip is the core of electrical meter. The accuracy of metering chip affects the measurement property of electrical meter, so it’s necessary to study the behavior of it. The simulation studies of metering chip are mostly based on part sections of it, but lack the whole simulation model. This paper proposes a Simulink model of whole metering chip based on certain one-phase metering chip by designing the ADC, high pass filter (HPF), low pass filter (LPF), and so on, and make simulation of this model. The result shows that the accuracy of this model is about 0.1%, which verifies the effectiveness of it.


2004 ◽  
Vol 43 (5A) ◽  
pp. 2786-2790 ◽  
Author(s):  
Han-Shin Lee ◽  
Dong-Hoon Shin ◽  
Sung-Chan Kim ◽  
Byeong-Ok Lim ◽  
Tae-Jong Baek ◽  
...  

2019 ◽  
Vol 2019 (1) ◽  
Author(s):  
Eric J. Balster ◽  
David B. Mundy ◽  
Andrew M. Kordik ◽  
Kerry L. Hill

AbstractIn this paper, a synthetic aperture radar (SAR) image formation simulator is used to objectively evaluate the parameter selection within the digital spotlighting process. Specifically, recommendations for the filter type and filter order of the low-pass filters used in the range and azimuth decimation processes within the digital spotlighting algorithm are determined to maximize image quality and minimize computational cost. Results show that a finite impulse response low-pass filter with a Taylor $(\overline {n}=5)$(n¯=5) window applied provides the highest image quality over a wide range of filter orders and decimation factors. Additionally, a linear relationship between filter length and decimation factor is found.


2017 ◽  
Vol E100.C (10) ◽  
pp. 858-865 ◽  
Author(s):  
Yohei MORISHITA ◽  
Koichi MIZUNO ◽  
Junji SATO ◽  
Koji TAKINAMI ◽  
Kazuaki TAKAHASHI

Sign in / Sign up

Export Citation Format

Share Document