Efficient layout data compression algorithm and its low-complexity, high-performance hardware decoder implementation for multiple electron-beam direct-write systems

2015 ◽  
Vol 14 (3) ◽  
pp. 031212 ◽  
Author(s):  
Chin-Khai Tang ◽  
Ming-Shing Su ◽  
Yi-Chang Lu
Keyword(s):  
Electron Beam ◽  
Data Compression ◽  
High Performance ◽  
Low Complexity ◽  
Compression Algorithm ◽  
Direct Write

Fast Block Matching Algorithm for Ray Space Data Compression

2013 ◽  
Vol 380-384 ◽  
pp. 1477-1481
Author(s):  
Zhi Peng Jin ◽  
Yu Yan Fang ◽  
Mei Yu
Keyword(s):  
Data Compression ◽  
High Performance ◽  
Texture Classification ◽  
Low Complexity ◽  
Block Matching ◽  
Matching Algorithm ◽  
Block Matching Algorithm ◽  
Texture Characteristics ◽  
Template Selection ◽  
Space Data

in order to improve the efficiency of ray-space data compression, according to the texture characteristics of ray space data, introducing a simple effective method of texture classification, a new fast block matching algorithm based on adaptive template selection is proposed in this paper, for prediction coding of ray space slice sequence. Experimental results show that the proposed algorithm has low-complexity and high-performance characteristics, for different types of ray space slice sequences with strong adaptability.

scholarly journals Solution‐Processed High‐Performance ZnO Nano‐FETs Fabricated with Direct‐Write Electron‐Beam‐Lithography‐Based Top‐Down Route

2021 ◽  
pp. 2000978
Author(s):  
Nikhil Tiwale ◽  
Satyaprasad P. Senanayak ◽  
Juan Rubio‐Lara ◽  
Abhinav Prasad ◽  
Atif Aziz ◽  
...  
Keyword(s):  
Electron Beam ◽  
Electron Beam Lithography ◽  
High Performance ◽  
Direct Write ◽  
Top Down ◽  
Solution Processed

ELECTRON BEAM DIRECT WRITE EFFECTS ON CMOS DEVICES

1988 ◽  
Vol 49 (C4) ◽  
pp. C4-291-C4-294
Author(s):  
K. BARLOW
Keyword(s):  
Electron Beam ◽  
Direct Write

Properties of High-Performance Porous SiOC Low-kFilm Fabricated Using Electron-Beam Curing

2005 ◽  
Vol 44 (6A) ◽  
pp. 3872-3878 ◽  
Author(s):  
Takashi Yoda ◽  
Keiji Fujita ◽  
Hideshi Miyajima ◽  
Rempei Nakata ◽  
Naoto Miyashita ◽  
...  
Keyword(s):  
Electron Beam ◽  
High Performance ◽  
Electron Beam Curing

scholarly journals Expanding 3D Nanoprinting Performance by Blurring the Electron Beam

Micromachines ◽  
2021 ◽  
Vol 12 (2) ◽  
pp. 115
Author(s):  
Lukas Seewald ◽  
Robert Winkler ◽  
Gerald Kothleitner ◽  
Harald Plank
Keyword(s):  
Electron Beam ◽  
Direct Write ◽  
Design Flexibility ◽  
Individual Branch ◽  
Inclination Angles ◽  
3D Architecture ◽  
20 Nm ◽  
Surface Morphologies ◽  
Nm Range ◽  
Mechanical Rigidity

Additive, direct-write manufacturing via a focused electron beam has evolved into a reliable 3D nanoprinting technology in recent years. Aside from low demands on substrate materials and surface morphologies, this technology allows the fabrication of freestanding, 3D architectures with feature sizes down to the sub-20 nm range. While indispensably needed for some concepts (e.g., 3D nano-plasmonics), the final applications can also be limited due to low mechanical rigidity, and thermal- or electric conductivities. To optimize these properties, without changing the overall 3D architecture, a controlled method for tuning individual branch diameters is desirable. Following this motivation, here, we introduce on-purpose beam blurring for controlled upward scaling and study the behavior at different inclination angles. The study reveals a massive boost in growth efficiencies up to a factor of five and the strong delay of unwanted proximal growth. In doing so, this work expands the design flexibility of this technology.

scholarly journals High Area-Efficient Parallel Encoder with Compatible Architecture for 5G LDPC Codes

Symmetry ◽  
2021 ◽  
Vol 13 (4) ◽  
pp. 700
Author(s):  
Yufei Zhu ◽  
Zuocheng Xing ◽  
Zerun Li ◽  
Yang Zhang ◽  
Yifan Hu
Keyword(s):  
High Performance ◽  
Ldpc Codes ◽  
Low Complexity ◽  
Cmos Technology ◽  
Area Efficiency ◽  
Prior Art ◽  
New Radio ◽  
High Area ◽  
Significant Area ◽  
Area Efficient

This paper presents a novel parallel quasi-cyclic low-density parity-check (QC-LDPC) encoding algorithm with low complexity, which is compatible with the 5th generation (5G) new radio (NR). Basing on the algorithm, we propose a high area-efficient parallel encoder with compatible architecture. The proposed encoder has the advantages of parallel encoding and pipelined operations. Furthermore, it is designed as a configurable encoding structure, which is fully compatible with different base graphs of 5G LDPC. Thus, the encoder architecture has flexible adaptability for various 5G LDPC codes. The proposed encoder was synthesized in a 65 nm CMOS technology. According to the encoder architecture, we implemented nine encoders for distributed lifting sizes of two base graphs. The eperimental results show that the encoder has high performance and significant area-efficiency, which is better than related prior art. This work includes a whole set of encoding algorithm and the compatible encoders, which are fully compatible with different base graphs of 5G LDPC codes. Therefore, it has more flexible adaptability for various 5G application scenarios.

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