A low-cost (with bare chips) and high (electrical, thermal, and mechanical) performance 3D IC integration system-in-package (SiP) is designed and described. This system consists of a silicon interposer with through-silicon vias (TSV) [1–24] and redistribution layers (RDL), which carries the high-power flip chips with microbumps on its top surface and the low-power chips at its bottom surface. TSVs in the high- and low-power chips are optional but should be avoided. The backside of the high-power chips is attached to a heat spreader with or w/o a heat sink. This 3D IC integration system is supported (packaged) by a simple conventional organic substrate. The heat spreader (with or w/o heat sink) and the substrate are connected by a ring stiffener, which provides adequate standoff for the 3D IC integration system. This novel structural design offers potential solutions for high-power, high-performance, high pin-count, ultra fine-pitch, small real-estate, and low-cost applications. Thermal management and reliability of the proposed systems are demonstrated by simulations based on heat-transfer theory and time and temperature dependent creep theory.
Low-power gated bus synthesis for 3d ic via rectilinear shortest-path steiner graph