Analysis of Degradation Mechanisms of Gate Dielectrics Based on SiO2 in MOS Transistors

2021 ◽  
Author(s):  
D. A. Eliseeva ◽  
S. O. Safonov
Keyword(s):  
Gate Dielectrics ◽  
Degradation Mechanisms ◽  
Mos Transistors

Effect of Technology Scaling on MOS Transistor Performance with High-K Gate Dielectrics

2002 ◽  
Vol 716 ◽  
Author(s):  
Nihar R. Mohapatra ◽  
Madhav P. Desai ◽  
Siva G. Narendra ◽  
V. Ramgopal Rao
Keyword(s):  
Gate Dielectric ◽  
Gate Dielectrics ◽  
Channel Length ◽  
Mos Transistors ◽  
Short Channel ◽  
Technology Scaling ◽  
Mos Transistor ◽  
Wide Range ◽  
Impact Of Technology ◽  
The Impact

AbstractThe impact of technology scaling on the MOS transistor performance is studied over a wide range of dielectric permittivities using two-dimensional (2-D) device simulations. It is found that the device short channel performance is degraded with increase in the dielectric permittivity due to an increase in dielectric physical thickness to channel length ratio. For Kgate greater than Ksi, we observe a substantial coupling between source and drain regions through the gate dielectric. We provide extensive 2-D device simulation results to prove this point. Since much of the coupling between source and drain occurs through the gate dielectric, it is observed that the overlap length is an important parameter for optimizing DC performance in the short channel MOS transistors. The effect of stacked gate dielectric and spacer dielectric on the MOS transistor performance is also studied to substantiate the above observations.

Carrier separation analysis for clarifying carrier conduction and degradation mechanisms in high-k stack gate dielectrics

2005 ◽  
Vol 45 (7-8) ◽  
pp. 1041-1050 ◽  
Author(s):  
Wataru Mizubayashi ◽  
Naoki Yasuda ◽  
Kenji Okada ◽  
Hiroyuki Ota ◽  
Hirokazu Hisamatsu ◽  
...  
Keyword(s):  
Gate Dielectrics ◽  
Degradation Mechanisms ◽  
High K ◽  
Carrier Separation

Analysis of Degradation Mechanisms of Gate Dielectrics Based on SiO2 in MOS Transistors

2020 ◽  
Vol 25 (6) ◽  
pp. 517-524
Author(s):  
D.A. Eliseeva ◽  
◽  
S.O. Safonov ◽  
◽  
Keyword(s):  
Mathematical Models ◽  
Gate Dielectric ◽  
Gate Dielectrics ◽  
Degradation Mechanism ◽  
Operating Time ◽  
Operating Conditions ◽  
Hole Injection ◽  
Operating Voltage ◽  
Mos Transistors ◽  
The Impact

Nowadays, the developed mathematical models, describing the degradation mechanism of the gate dielectric, permit to determine the value of the operating time to failure of a device depending on its internal properties and operating conditions. These models significantly reduce the time and material required for performing testing and processing of large amounts of experimental data. In the paper the gate dielectric gates based on SiO in n -and p -channel MOS transistors have been studied. It has been found that under the impact of the electric field the degradation of the gate dielectric with 5.3 nm thickness most likely occurs according to the thermochemical model ( E -model) and in case with 7 nm thickness dielectric- in accordance with the anode hole injection model (1/ E -model). The coefficients have been calculated and the analysis of the mathematical models, permitting to determine the service life gate dielectrics based on SiO with 7 nm thickness in n - and p -channel MOS transistors for different values, of their area, operating voltage and temperature, has been performed. This study can serve as a method for monitoring and determining the quality of the gate dielectrics of manufactured MOS transistors.

The Influence of Fluorine on Various Mos Devices

1999 ◽  
Vol 567 ◽  
Author(s):  
G. Innertsberger ◽  
R. Jurk ◽  
J. Felsner ◽  
R. Kakoschke ◽  
B. Yuwono ◽  
...  
Keyword(s):  
Gate Dielectrics ◽  
Fluorine Content ◽  
Fluorine Concentration ◽  
Mos Transistors ◽  
Mos Transistor ◽  
Bias Temperature Instability ◽  
Non Volatile Memory ◽  
The One ◽  
Soft Breakdown

ABSTRACTThe influence of Vapor Phase Precleans leads to a different controllable fluorine content within the subsequently grown dielectric. The influence of the clean is discussed for non-volatile memory devices, advanced MOS transistors and ultra thin gate dielectrics. On the one hand, the Qbd values for in situ cleaned samples are lower than for wet cleaned samples. Performing cycle stress on the EEPROM devices, the tunnel oxide (7.5nm) degrades the quicker with the increase in fluorine concentration within the oxide. On the other hand, MOS transistor characteristics show a significant improvement on the negative bias temperature instability (NBTI) in the PMOS threshold voltage. MOS transistors with ultra thin gate dielectrics (1.5nm) show the expected significant increase of the saturation current compared with 0.35µm technology (tox = 7.5nm). Excellent times until soft breakdown for ultra thin dielectrics are found when the in situ cleaning is used.

High Mobility Dual Metal Gate MOS Transistors with High-k Gate Dielectrics

2004 ◽  
Author(s):  
Kensuke Takahashi ◽  
Kenzo Manabe ◽  
Ayuka Morioka ◽  
Taeko Ikarashi ◽  
Takuya Yoshihara ◽  
...  
Keyword(s):  
Gate Dielectrics ◽  
High Mobility ◽  
Mos Transistors ◽  
Metal Gate ◽  
High K ◽  
Dual Metal

Polarity Dependence of Degradation in Ultra Thin Oxide and JVD Nitride Gate Dielectrics

2002 ◽  
Vol 716 ◽  
Author(s):  
Yatin Mutha ◽  
K.N. ManjulaRani ◽  
Rakesh Lal ◽  
V.Ramgopal Rao
Keyword(s):  
High Field ◽  
Gate Dielectrics ◽  
Stress Conditions ◽  
Stress Fields ◽  
Degradation Mechanisms ◽  
Detailed Characterization ◽  
Offset Voltage ◽  
Thin Oxide ◽  
Hole Recombination ◽  
Dc Stress

AbstractWe have studied high field degradation of Jet Vapor Deposited (JVD) silicon nitride MNSFETs with DC stress fields and compared their degradation with conventional silicon dioxide MOSFETs under identical stress conditions. We have observed that in both oxide and nitride devices, the interface degradation is higher for negative gate field. Further, the relative degradation of nitrides is always lower compared to that of oxides for both positive and negative stress conditions. AC stress experiments were performed on these ultra thin oxide transistors to understand possible degradation processes. The frequency, the peak-to-peak and offset voltage of the applied AC signal are some of the parameters that have been varied. Detailed characterization results and an analysis of the degradation mechanisms are presented in this paper. We conclude that many of the degradation results can be explained using the trapped hole recombination model.

High-Mobility Dual Metal Gate MOS Transistors with High-k Gate Dielectrics

2005 ◽  
Vol 44 (4B) ◽  
pp. 2210-2213 ◽  
Author(s):  
Kensuke Takahashi ◽  
Kenzo Manabe ◽  
Ayuka Morioka ◽  
Taeko Ikarashi ◽  
Takuya Yoshihara ◽  
...  
Keyword(s):  
Gate Dielectrics ◽  
High Mobility ◽  
Mos Transistors ◽  
Metal Gate ◽  
High K ◽  
Dual Metal
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