EARLY BUFFER PLANNING WITH CONGESTION CONTROL USING BUFFER REQUIREMENT MAP

2010 ◽  
Vol 19 (05) ◽  
pp. 949-973
Author(s):  
ALI JAHANIAN ◽  
MORTEZA SAHEB ZAMANI
Keyword(s):  
Signal Integrity ◽  
Deep Submicron ◽  
Design Flow ◽  
Buffer Insertion ◽  
Design Quality ◽  
Circuit Performance ◽  
Buffer Planning ◽  
Planning Algorithm ◽  
Buffer Requirement ◽  
Time Overhead

Buffer insertion plays an important role in circuit performance and signal integrity especially in deep submicron technologies. The stage at which buffers are inserted in a design has a large impact on the design quality. Early buffer insertion may cause misestimation due to unknown cell locations whereas buffer insertion after placement may not be very effective because the cell locations have been fixed and buffer resources may be distributed inappropriately. In this paper, a buffer planning algorithm for floor-placement design flow is presented. This algorithm creates a map of buffer requirements in various regions of the design at the floorplanning stage and then enforces the detailed placer to distribute white spaces with respect to the estimated buffer requirement map. Experimental results show that the proposed method improves the performance of attempted circuits with fewer buffers. Furthermore, results show that congestion, routability and design convergence are improved and the auxiliary loops are avoided in the proposed design flow. Our analyses and experiments show that the CPU time overhead of this algorithm is very small.

Statistical Gate-Delay Modeling with Copulas

2020 ◽  
Vol 15 (3) ◽  
pp. 1-10
Author(s):  
Walter Schneider
Keyword(s):  
Circuit Design ◽  
Integrated Circuit ◽  
Process Variations ◽  
Deep Submicron ◽  
Experimental Results ◽  
Gate Delay ◽  
Integrated Circuit Design ◽  
Circuit Performance ◽  
Delay Models ◽  
Innovative Concept

The growing impact of process variations on circuit performance has become a major concern for deep-submicron integrated circuit design, resulting in numerous SSTA-algorithms. The acceptance of such algorithms in industry however will be dependent on modeling the real silicon behavior in SSTA. This includes that the statistical gate-delay models must consider arbitrary process variations and dependencies. In this paper, we introduce the innovative concept of Copulas to handle this topic. A complete Matlab based framework starting from process parameter statistics up to the computation of the statistical gate-delay distribution is presented. Experimental results demonstrate the importance of accounting realistic process variations.

scholarly journals Shedding Physical Synthesis Area Bloat

VLSI Design ◽  
2011 ◽  
Vol 2011 ◽  
pp. 1-10 ◽  
Author(s):  
Ying Zhou ◽  
Charles J. Alpert ◽  
Zhuo Li ◽  
Cliff Sze ◽  
Louise H. Trevillyan
Keyword(s):  
Power Dissipation ◽  
Design Flow ◽  
Low Power Consumption ◽  
Gate Sizing ◽  
Buffer Insertion ◽  
Growth Reduction ◽  
Timing Closure ◽  
Area Reduction ◽  
Area Increase ◽  
Physical Synthesis

Area bloat in physical synthesis not only increases power dissipation, but also creates congestion problems, forces designers to enlarge the die area, rerun the whole design flow, and postpone the design deadline. As a result, it is vital for physical synthesis tools to achieve timing closure and low power consumption with intelligent area control. The major sources of area increase in a typical physical synthesis flow are from buffer insertion and gate sizing, both of which have been discussed extensively in the last two decades, where the main focus is individual optimized algorithm. However, building a practical physical synthesis flow with buffering and gate sizing to achieve the best timing/area/runtime is rarely discussed in any previous literatures. In this paper, we present two simple yet efficient buffering and gate sizing techniques and achieve a physical synthesis flow with much smaller area bloat. Compared to a traditional timing-driven flow, our work achieves 12% logic area growth reduction, 5.8% total area reduction, 10.1% wirelength reduction, and 770 ps worst slack improvement on average on 20 industrial designs in 65 nm and 45 nm.

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