A SEAMLESS-CONTROLLED DIGITAL PLL USING DUAL LOOPS FOR HIGH SPEED SOCS

2011 ◽  
Vol 20 (04) ◽  
pp. 741-756 ◽  
Author(s):  
YOUNG SAN SHIN ◽  
JAE-KYUNG WEE ◽  
JONG-CHAN HA ◽  
JI-HOON LIM ◽  
YONG-JU KIM ◽  
...  
Keyword(s):  
Power Dissipation ◽  
High Speed ◽  
Phase Error ◽  
Cmos Technology ◽  
Digital To Analog Converter ◽  
Frequency Tracking ◽  
Operating Frequency Range ◽  
Analog Converter ◽  
Lock In ◽  
Wide Operating

A new dual-loop digital phased-locked loop (DPLL) architecture is presented. This novel architecture is designed to provide a wide operating frequency range, high precision, and small jitter, and fits over a relatively small area. To achieve these characteristics, the architecture is implemented using a coarse loop with an UP/DOWN counter and a coarse digital-to-analog converter (DAC) to rapidly reduce the phase error, and a fine loop with a time-to-digital converter (TDC) and a fine DAC to provide more precision. Furthermore, the seamless-frequency tracking architecture based on a code conversion between the coarse cell and the fine cell of the DAC is devised to improve the lock-in stability. The chip is fabricated with Dongbu HiTek 0.18-μm CMOS technology. It has a wide operation range of 0.4–1.4 GHz, and an area of 0.195 mm2. The measured results show 15.64 ps peak-to-peak jitter and 2.22 ps rms jitter, and a power dissipation of 16.2 mW at 1 GHz.

Two-Dimensional Structure Compatible with DEM Methods Utilizing in DACs

2018 ◽  
Vol 27 (09) ◽  
pp. 1850142 ◽  
Author(s):  
Mehdi Bandali ◽  
Omid Hashemipour
Keyword(s):  
Dynamic Range ◽  
Cmos Technology ◽  
Dimensional Structure ◽  
Signal Frequency ◽  
Two Dimensional ◽  
Dynamic Element Matching ◽  
Digital To Analog Converter ◽  
Spurious Free Dynamic Range ◽  
Analog Converter ◽  
Free Dynamic

A two-dimensional digital-to-analog converter (DAC) structure compatible with dynamic element matching (DEM) methods is presented. Unlike the DACs using segmented structure for employing DEM, the new structure randomizes inter-segment error. This advantage is achieved because of the characteristics of the algorithm of two-dimensional decoding. The simulation results in 180[Formula: see text]nm CMOS technology, 319.72[Formula: see text]MHz signal frequency and 800[Formula: see text]MS/s sample rate for an 8-bit two-dimensional DAC utilizing the presented structure, shows 14.94[Formula: see text]dB spurious-free dynamic range (SFDR) improvement compared to the SFDR of the same DAC without employing the presented structure. Also, the IMD3 of the DAC employing the presented structure for [Formula: see text][Formula: see text]MHz and [Formula: see text][Formula: see text]MHz is 50.1[Formula: see text]dB.

A Noise Reduction 12-bit 125-MSPS SAR ADC with Modified Asynchronous Logic Regulation Technique

2020 ◽  
pp. 2150040
Author(s):  
Daiguo Xu ◽  
Han Yang ◽  
Xing Sheng ◽  
Ting Sun ◽  
Guangbing Chen ◽  
...  
Keyword(s):  
Noise Reduction ◽  
Feedback Loop ◽  
Cmos Technology ◽  
Sar Adc ◽  
Dynamic Comparator ◽  
Digital To Analog Converter ◽  
Analog To Digital ◽  
Asynchronous Logic ◽  
Analog Converter ◽  
Nyquist Rate

This paper presents noise reduction and modified asynchronous logic regulation techniques used in successive approximation register (SAR) analog-to-digital converter (ADC). With a transconductance enhanced structure, noise reduction is provided in the dynamic comparator. The input referred noise of the proposed comparator is about 165[Formula: see text][Formula: see text]V rms at 60∘C (typical corner). An enhanced-positive-feedback loop is introduced to reduce the regeneration delay of the comparator. In addition, a modified asynchronous logic regulation technique is exhibited, a clock with adaptable delay is driving the comparator in approximation phase. Consequently, the settling accuracy of DAC (Digital-to-Analog Converter) is enough and the conversion speed of SAR ADC is increased without any redundant cycles. To demonstrate the proposed techniques, a design of SAR ADC is fabricated in 65-nm CMOS technology, consuming 4[Formula: see text]mW from 1.2[Formula: see text]V power supply with a [Formula: see text][Formula: see text]dB and [Formula: see text][Formula: see text]dB. The proposed ADC core occupies an active area of 0.048[Formula: see text]mm2, and the corresponding FoM is 27.2[Formula: see text]fJ/conversion-step at Nyquist rate.

Low-power 8-bit 5-GS/s digital-to-analog converter for multi-gigabit wireless transceivers

2012 ◽  
Vol 4 (3) ◽  
pp. 275-282 ◽  
Author(s):  
Behnam Sedighi ◽  
Mahdi Khafaji ◽  
Johann Christoph Scheytt
Keyword(s):  
Low Power ◽  
High Speed ◽  
Wireless Transceivers ◽  
Digital To Analog Converter ◽  
Bicmos Technology ◽  
Analog Converter ◽  
Sige Bicmos ◽  
Digital To Analog ◽  
On Chip ◽  
Binary Weighted

We present a method to realize a low-power and high-speed digital-to-analog converter (DAC) for system-on-chip applications. The new method is a combination of binary-weighted current cells and R-2R ladder and is specially suited for modern BiCMOS technologies. A prototype 5 GS/s DAC is implemented in 0.13 μm SiGe BiCMOS technology. The DAC dissipates 26 mW and provides an SFDR higher than 48 dB for output frequencies up to 1 GHz.

TID Effects on 12-Bit Digital-to-Analog Converter

2013 ◽  
Vol 677 ◽  
pp. 326-333
Author(s):  
Xue Wu ◽  
Wu Lu ◽  
Qi Guo
Keyword(s):  
Elevated Temperature ◽  
High Speed ◽  
Room Temperature ◽  
Irradiation Effects ◽  
Ionizing Irradiation ◽  
Digital To Analog Converter ◽  
Annealing Behavior ◽  
Analog Converter ◽  
Before And After ◽  
Digital To Analog

This Paper describes ionizing irradiation effects and annealing behavior on some commercial available CMOS high speed and high resolution Digital-to-Analog Converter —AD9742. AC and DC parameters are measured before and after radiation and annealing experiment. Results show that DC parameters are more sensitive than AC parameters, and all parameters are fully recovered after room-temperature and elevated-temperature annealing behaviors. Test facilities, results and analysis are presented in this paper in details.

scholarly journals Low Power VLSI Design Techniques: A Review

2021 ◽  
Vol 23 (11) ◽  
pp. 172-183
Author(s):  
Ketan J. Raut ◽  
◽  
Abhijit V. Chitre ◽  
Minal S. Deshmukh ◽  
Kiran Magar ◽  
...  
Keyword(s):  
Low Power ◽  
Power Dissipation ◽  
High Speed ◽  
Vlsi Design ◽  
Cmos Technology ◽  
Vlsi Circuits ◽  
Optimization Techniques ◽  
Battery Life ◽  
Dynamic Power ◽  
Cmos Vlsi

Since CMOS technology consumes less power it is a key technology for VLSI circuit design. With technologies reaching the scale of 10 nm, static and dynamic power dissipation in CMOS VLSI circuits are major issues. Dynamic power dissipation is increased due to requirement of high speed and static power dissipation is at much higher side now a days even compared to dynamic power dissipation due to very high gate leakage current and subthreshold leakage. Low power consumption is equally important as speed in many applications since it leads to a reduction in the package cost and extended battery life. This paper surveys contemporary optimization techniques that aims low power dissipation in VLSI circuits.

scholarly journals Non-Linear Mathematical Modelling for Phase Locked Loop

2018 ◽  
Vol 7 (4.10) ◽  
pp. 81
Author(s):  
Prithiviraj R ◽  
Selvakumar J
Keyword(s):  
High Speed ◽  
Linear Models ◽  
Low Cost ◽  
Phase Error ◽  
Phase Locked Loop ◽  
Cmos Technology ◽  
Low Noise ◽  
Voltage Controlled Oscillator ◽  
Loop Filter ◽  
Non Linear

Design of Phase Locked Loop (PLL) plays a vital role in transceiver field. Phase Locked Loop comprises of three blocks, namely Phase and frequency detector, loop filter and voltage-controlled oscillator. The greater advancements in CMOS technology such as high frequency, high speed, low noise and phase error leads to low-cost PLL This work aims to develop higher order non-linear models of general Phase Locked Loop. The condition of stability and choice of loop filter is also determined. Based on the analysis, the transfer function for PLL is determined.  

Sign in / Sign up

Export Citation Format

Share Document