scholarly journals Low Power VLSI Design Techniques: A Review

2021 ◽  
Vol 23 (11) ◽  
pp. 172-183
Author(s):  
Ketan J. Raut ◽  
◽  
Abhijit V. Chitre ◽  
Minal S. Deshmukh ◽  
Kiran Magar ◽  
...  
Keyword(s):  
Low Power ◽  
Power Dissipation ◽  
High Speed ◽  
Vlsi Design ◽  
Cmos Technology ◽  
Vlsi Circuits ◽  
Optimization Techniques ◽  
Battery Life ◽  
Dynamic Power ◽  
Cmos Vlsi

Since CMOS technology consumes less power it is a key technology for VLSI circuit design. With technologies reaching the scale of 10 nm, static and dynamic power dissipation in CMOS VLSI circuits are major issues. Dynamic power dissipation is increased due to requirement of high speed and static power dissipation is at much higher side now a days even compared to dynamic power dissipation due to very high gate leakage current and subthreshold leakage. Low power consumption is equally important as speed in many applications since it leads to a reduction in the package cost and extended battery life. This paper surveys contemporary optimization techniques that aims low power dissipation in VLSI circuits.

scholarly journals Analysis On Power Gating Circuits Based Low Power VLSI Circuits (BCD Adder)

2021 ◽  
Vol 2089 (1) ◽  
pp. 012080
Author(s):  
M. Srinivas ◽  
K.V. Daya Sagar
Keyword(s):  
Energy Consumption ◽  
Low Power ◽  
Power Dissipation ◽  
Supply Voltage ◽  
Oxide Thickness ◽  
Cmos Technology ◽  
Digital Circuit ◽  
Leakage Power ◽  
Vlsi Circuits ◽  
Battery Life

Abstract Currently, energy consumption in the digital circuit is a key design parameter for emerging mobile products. The principal cause of the power dissipation during idle mode is leakage currents, which are rising dramatically. Sub-threshold leakage is increased by the scaling of threshold voltage when gate current leakage increases because oxide thickness is scaled. With rising demands for mobile devices, leakage energy consumption has received even greater attention. Since a mobile device spends most of its time in standby mode, leakage power savings need to prolong the battery life. That is why low power has become a significant factor in CMOS circuit design. The required design and simulation of an AND gate with the BSIM4 MOS parameter model at 27 0C, supply voltage of 0,70V with CMOS technology of 65nm are the validation of the suitability of the proposed circuit technology. AND simulation. The performance parameters for the two AND input gate are compared with the current MTCMOS and SCCMOS techniques, such as sub-threshold leakage power dissipations in active and standby modes, the dynamic dissipation, and propagation period. The proposed hybrid super cutoff complete stack technique compared to the current MTCMOS technology shows a reduction in sub-threshold dissipation power dissipation by 3. 50x and 1.15x in standby modes and active modes respectively. The hybrid surface-cutting technique also shows savings of 2,50 and 1,04 in power dissipation at the sub-threshold in standby modes and active modes compared with the existing SCCMOS Technique.

scholarly journals Design of Low Power and High Speed 4X4 Multiplier using Modified Column Bypassing Scheme for DSP Applications

2019 ◽  
Vol 8 (2S3) ◽  
pp. 643-647
Keyword(s):  
Low Power ◽  
Digital Signal Processor ◽  
High Speed ◽  
Vlsi Design ◽  
Digital Signal ◽  
Cmos Technology ◽  
Optimization Techniques ◽  
Operating Voltage ◽  
Booth Encoder ◽  
Dsp Applications

In this paper a low power and high speed 4X4 multiplier is designed using CMOS Technology. The important factors in VLSI Design are power, area, speed and design time. Now-a-days, power and speed has become a crucial factor in Digital Signal Processor (DSP) Applications. However, different optimization techniques are available in the digital electronic world. The proposed approach a Low power and high speed Multiplier Design based on Modified Column bypassing technique mainly used to reduce the switching power activity. While this technique offers great dynamic power savings, due to their interconnection. In this work, a low power and high speed multiplier with Hybridization scheme is presented. This scheme is combination of booth encoder algorithm and column bypass technique is called modified column bypassing scheme. The simulations are performed in 0.18µm CMOS Technology in Cadence Virtuoso tools with operating voltage ±1.8v

scholarly journals Power optimization of binary division based on FPGA

2021 ◽  
Vol 24 (3) ◽  
pp. 1354
Author(s):  
Fadi T. Nasser ◽  
Ivan A. Hashim
Keyword(s):  
Low Power ◽  
Power Dissipation ◽  
High Speed ◽  
Large Scale ◽  
Power Optimization ◽  
Optimization Technique ◽  
Optimization Techniques ◽  
Digital Systems ◽  
Dynamic Power ◽  
System Designs

In modern very large scale integrated (VLSI) digital systems, power consumption has become a critical concern of VLSI designers. As size shrinks and density increases in chips, it will be a challenge to design high performance and low-power digital systems. Therefore, VLSI designers are trying to reduce power dissipation in these systems by using power optimization techniques. Different mathematical operations can be found in the architectures of most digital systems. The focus of this paper is division. In comparison to other basic computational operations, division requires more iterations, takes a long time, covers a large area, and consumes more power from the digital system. As a result, the system's design requires high speed and a low-power divider in order to improve its overall performance. This paper focuses on dynamic power dissipation. In order to determine which design consumes the lowest dynamic power, different system designs of digit-recurrence division algorithms, such as restoring division and non-restoring division are suggested. An innovative power-optimization technique, the very hardware descriptions language (VHDL) technique, is utilized to the suggested system designs. The VHDL technique achieved the higher optimization in dynamic power, at 93.66% for non-restoring division with internal-loop iteration, than traditional approaches.

scholarly journals A HIGH-PERFORMANCE AND LOW-POWER DELAY BUFFER

2013 ◽  
pp. 78-82
Author(s):  
GOPALA KRISHNA.M ◽  
UMA SANKAR.CH ◽  
NEELIMA. S ◽  
KOTESWARA RAO.P
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
High Speed ◽  
High Performance ◽  
Vlsi Design ◽  
Flip Flop ◽  
Ring Counter ◽  
Double Edge ◽  
Low Power Cmos ◽  
Cmos Vlsi

In this paper, presents circuit design of a low-power delay buffer. The proposed delay buffer uses several new techniques to reduce its power consumption. Since delay buffers are accessed sequentially, it adopts a ring-counter addressing scheme. In the ring counter, double-edge-triggered (DET) flip-flops are utilized to reduce the operating frequency by half and the C-element gated-clock strategy is proposed. Both total transistor count and the number of clocked transistors are significantly reduced to improve power consumption and speed in the flip-flop. The number of transistors is reduced by 56%-60% and the Area-Speed-Power product is reduced by 56%-63% compared to other double edge triggered flip-flops. This design is suitable for high-speed, low-power CMOS VLSI design applications.

scholarly journals Encoding Schemes for Reducing Transition Activity and Power Consumption in VLSI Interconnects-A Review

2018 ◽  
Vol 7 (3.1) ◽  
pp. 34
Author(s):  
Vithyalakshmi. N ◽  
Nagarajan P ◽  
Ashok Kumar.N ◽  
Vinoth. G.S
Keyword(s):  
Energy Dissipation ◽  
Power Consumption ◽  
Low Power ◽  
Vlsi Design ◽  
Low Power Design ◽  
System Size ◽  
Vlsi Circuits ◽  
Portable Devices ◽  
Dynamic Power ◽  
Transition Activity

Low power design is a foremost challenging issue in recent applications like mobile phones and portable devices. Advances in VLSI technology have enabled the realization of complicated circuits in single chip, reducing system size and power utilization. In low power VLSI design energy dissipation has to be more significant. So to minimize the power consumption of circuits various power components and their effects must be identified. Dynamic power is the major energy dissipation in micro power circuits. Bus transition activity is the major source of dynamic power consumption in low power VLSI circuits. The dynamic power of any complex circuits cannot be estimated by the simple calculations. Therefore this paper review different encoding schemes for reduction of transition activity and power dissipation. 

scholarly journals Efficient Low Power/Low Swing Bus Design Architectures

VLSI Design ◽  
2001 ◽  
Vol 12 (3) ◽  
pp. 415-429
Author(s):  
Abdoul Rjoub ◽  
Odysseas Koufopavlou
Keyword(s):  
Low Power ◽  
Threshold Voltage ◽  
Power Dissipation ◽  
High Speed ◽  
Cmos Technology ◽  
Variable Number ◽  
High Load ◽  
Nmos Transistor ◽  
The Difference ◽  
Full Swing

Novel low-power circuits based on low swing voltage technique, in the internal nodes of bus architectures, are proposed. Different classes of driver/receiver and repeater circuits are presented. They are implemented on conventional CMOS technology. The proposed technique is based on inserting a variable number of MOSFET transistors in the driver circuits, causing variable low swing voltage levels in the output of the driver circuits. In order to re-pull up the low swing voltage to full swing, innovated high-speed, crosscoupled latch voltage receiver circuits are proposed. In applications having high load capacitance due to long interconnections, novel repeater circuits, based also on low swing voltage technique, are introduced. The difference between the values of threshold voltage of the nMOS transistor and the pMOS transistors is exploited to decrease the power dissipation. The effect of the proposed technique in noise margins is also analysed.

Design of (2, 1, N) Parallel Convolutional Encodes for VLSI

2013 ◽  
Vol 321-324 ◽  
pp. 2822-2827 ◽  
Author(s):  
Mao Qiang Duan ◽  
Xiao Li Huang
Keyword(s):  
Low Power ◽  
Power Dissipation ◽  
High Speed ◽  
Hardware Design ◽  
Cmos Technology ◽  
Shift Register ◽  
Vlsi Implementation ◽  
Parallel Method ◽  
Parallel Circuits ◽  
Low Power Dissipation

The characters of more high speed computing and much less low power dissipation are needed to settle for convolutional encodes. In this paper, we present a parallel method for convolutional encodes with SMIC 0.35μm CMOS technology; hardware design and VLSI implementation of this algorithm are also presented. Use this method, parallel circuits structure can be easily designed, which take on excellent characters of more high speed computing and low power dissipation compared with traditional serial shift register structure for convolutional encodes.

A Radix-16 Booth Multiplier Based on Recoding Adder with Ultra High Power Efficiency and Reduced Complexity for Neuroimaging

2020 ◽  
Vol 10 (4) ◽  
pp. 814-821
Author(s):  
J. Sureshbabu ◽  
G. Saravanakumar
Keyword(s):  
Low Power ◽  
Digital Signal Processor ◽  
Power Dissipation ◽  
Power Efficiency ◽  
High Speed ◽  
Average Power ◽  
Vlsi Design ◽  
Propagation Time ◽  
Power Gating ◽  
Booth Multiplier

In the current medical developments the neuro imaging plays a vital role in the study of a human brain related disorders. The accuracy of the brain study is mainly dependent on the images created from the scanners at a rapid speed. In achieving this we need a high speed and low power consuming scanners. The current scenario in VLSI design, the scanners highly rely on a high speed Digital Signal Processor (DSP), which generally depends on the speed of a multiplier. Multipliers are considered as a more complex component when compared with adders. The current techniques provide greater access to high-speed multipliers which are designed with less area that consume low power. The major constraints to be considered for an efficient multiplier design are propagation time delay and power dissipation, especially during the ideal time. An approximate recoding adder is proposed to reduce the existing booth multiplier's immensity. It increases the accuracy and reduces complexity through this technique; however, it has an issue with Power Delay Product (PDP) and power dissipation. To solve this problem, the proposed system is designed with a power gating based 16 × 16 bit Booth multiplier based on approximate recoding adder. It decreases the power dissipation and minimizes the length and width of the partial products for speeding up the multiplication process. The results obtained from the simulation show that the designed power gating based Radix multiplier circuits achieves better PDP, average power and area. The achieved results are compared with a Radix based multiplier, power gating CLA based multiplier and CLA based multiplier.

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