A MULTI-BAND LOW NOISE AMPLIFIER WITH GAIN FLATNESS AND BANDWIDTH ENHANCEMENT

In this paper, a differential multi-band CMOS low noise amplifier (LNA) is proposed that is operated within a range of 1500–2700 MHz with input matching capacitor switching and gain flatness performance enhancement technique. Traditional multi-band LNAs have poor performances on gain flatness performance. Therefore, we propose a new multi-band LNA which obtain good gain flatness performance by integrating the characteristics of the transistor trans-conductance and LC resonant load. The new LNA can also achieve a tunable frequency at different matching capacitance conditions. The post-layout simulation results shows that the voltage gain is between 19.3 dB and 22.4 dB, the NF is less than 2.5 dB, and the 1-dB compression point is about -5.1 dBm. The LNA consumes 17.79 mW under 1.8 V supply voltage in TSMC 0.18-um RF CMOS process.

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Wideband Input Matching CMOS Low-Noise Amplifier with Noise and Distortion Cancellation

Journal of Circuits System and Computers ◽

10.1142/s0218126620500590 ◽

2019 ◽

Vol 29 (04) ◽

pp. 2050059

Author(s):

Asieh Parhizkar Tarighat ◽

Mostafa Yargholi

Keyword(s):

Noise Figure ◽

Supply Voltage ◽

Low Noise ◽

Low Noise Amplifier ◽

Cmos Process ◽

Modified Technique ◽

Input Matching ◽

Noise Cancelling ◽

Resistive Feedback ◽

Noise Amplifier

In this paper, a wideband low-noise amplifier (LNA) is designed based on the resistive feedback topology with a TSMC 0.18[Formula: see text][Formula: see text]m standard RF CMOS process. Bandwidth expansion is provided by the second-order Chebyshev filter. The noise figure (NF) increases at high frequency because of the source parasitic capacitors of the cascode transistor; so, noise cancelling technique is applied to the cascode transistor of the proposed LNA. Bias conditions and sizes of the transistors are optimized to cancel the nonlinear transconductance ([Formula: see text]). With this modified technique, low noise figure, high linearity and improved input and output matching can be attained for 3.1–10.6[Formula: see text]GHz frequency band. Post-layout simulation result of the proposed LNA shows the maximum power gain of 17[Formula: see text]dB at 5.5[Formula: see text]GHz frequency, NF of lower than 4.5[Formula: see text]dB over the whole band of 3.1–10.6[Formula: see text]GHz, maximum IIP2 of [Formula: see text]28[Formula: see text]dBm and IIP3 of [Formula: see text]7.5[Formula: see text]dBm, while dissipating 9[Formula: see text]mW (with buffer) from a 1.8 V supply voltage. It occupies [Formula: see text]m silicon die area.

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Optimized Design of Low Power Complementary Metal Oxide Semiconductor Low Noise Amplifier for Zigbee Application

Journal of Computational and Theoretical Nanoscience ◽

10.1166/jctn.2021.9387 ◽

2021 ◽

Vol 18 (4) ◽

pp. 1327-1330

Author(s):

S. Manjula ◽

R. Karthikeyan ◽

S. Karthick ◽

N. Logesh ◽

M. Logeshkumar

Keyword(s):

Low Power ◽

Noise Figure ◽

Supply Voltage ◽

Low Noise ◽

Low Noise Amplifier ◽

Oxide Semiconductor ◽

Design System ◽

Cmos Process ◽

Design Specifications ◽

Noise Amplifier

An optimized high gain low power low noise amplifier (LNA) is presented using 90 nm CMOS process at 2.4 GHz frequency for Zigbee applications. For achieving desired design specifications, the LNA is optimized by particle swarm optimization (PSO). The PSO is successfully implemented for optimizing noise figure (NF) when satisfying all the design specifications such as gain, power dissipation, linearity and stability. PSO algorithm is developed in MATLAB to optimize the LNA parameters. The LNA with optimized parameters is simulated using Advanced Design System (ADS) Simulator. The LNA with optimized parameters produces 21.470 dB of voltage gain, 1.031 dB of noise figure at 1.02 mW power consumption with 1.2 V supply voltage. The comparison of designed LNA with and without PSO proves that the optimization improves the LNA results while satisfying all the design constraints.

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A FULLY INTEGRATED MULTIBAND CMOS 0.35 μM LNA FOR IEEE802.16 STANDARD

Journal of Circuits System and Computers ◽

10.1142/s0218126612500880 ◽

2013 ◽

Vol 22 (02) ◽

pp. 1250088 ◽

Cited By ~ 2

Author(s):

MERIAM BEN AMOR ◽

MOURAD LOULOU ◽

SEBASTIEN QUINTANEL ◽

DANIEL PASQUET

Keyword(s):

Noise Figure ◽

Supply Voltage ◽

Wide Band ◽

Low Noise ◽

Cmos Process ◽

Frequency Range ◽

Fully Integrated ◽

Input Matching ◽

Noise Amplifier ◽

Chebyshev Filter

In this paper we present the design of a fully integrated low noise amplifier for WiMAX standard with AMS 0.35 μm CMOS process. This LNA is designed to cover the frequency range for licensed and unlicensed bands of the WiMAX 2.3–5.9 GHz. The proposed amplifier achieves a wide band input and output matching with S11 and S22 lower than -10 dB, a flat gain of 12 dB and a noise figure around 3.5 dB for the entire band and from the upper to the higher frequencies. The presented wide band LNA employs a Chebyshev filter for input matching and an inductive shunt feedback for output matching with a bias current of 15 mA and a supply voltage of 2.5 V.

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An ESD Protected Wideband CMOS Low Noise Amplifier Employing Active Feedback Technique

Advanced Materials Research ◽

10.4028/www.scientific.net/amr.403-408.2809 ◽

2011 ◽

Vol 403-408 ◽

pp. 2809-2813

Author(s):

Kuan Bao ◽

Xiang Ning Fan

Keyword(s):

Noise Figure ◽

Low Noise ◽

Low Noise Amplifier ◽

Cmos Process ◽

Fully Integrated ◽

Input Matching ◽

Active Feedback ◽

Cmos Lna ◽

Noise Amplifier ◽

On Chip

This paper presents a wideband low noise amplifier (LNA) for multi-standard radio applications. The low noise characteristic and input matching are simultaneously achieved by active-feedback technique. Bond-wire inductors and electrostatic devices (ESDs) are co-designed to improve the chip performance. Implemented in 0.18-μm CMOS process, the core size of the fully integrated LNA circuits is 535 μm×425 μm without any passive on-chip inductor. The simulated gain and the minimal noise figure of the CMOS LNA are 17.5 dB and 2.0 dB, respectively. The LNA achieves a -3dB bandwidth of 3.1 GHz. And the simulated IIP3 is -4.4 dBm at 2.5 GHz. Operating at 1.8V, the LNA draws a current of 7.7 mA.

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Design of a Capacitor Cross-Coupled Common Gate Wideband Low Noise Amplifier with Noise Canceling Technique

Applied Mechanics and Materials ◽

10.4028/www.scientific.net/amm.618.548 ◽

2014 ◽

Vol 618 ◽

pp. 548-552

Author(s):

Dan Song ◽

Xiang Ning Fan ◽

Kuan Bao ◽

Zai Jun Hua

Keyword(s):

Noise Figure ◽

Supply Voltage ◽

Drain Current ◽

Low Noise ◽

Low Noise Amplifier ◽

Noise Characteristic ◽

Cmos Process ◽

Common Gate ◽

Noise Amplifier ◽

Noise Canceling

This paper presents a wideband low noise amplifier (LNA) for multi-standard radio application .The low noise amplifier achieves wideband matching with the structure of differential common gate .Meanwhile ,the low noise characteristic is achieved by noise canceling and capacitor cross-coupled. Fabricated in 0.18μm CMOS process, the LNA is designed to operate from 700MHz to 2.6GHz.As are shown in the results of simulation, when the LNA operates from 700MHz to 2.6GHz,the S11 is less than-10dB,the gain achieves 8.5 dB and the variation is within ±0.5dB.The noise figure is 2.2dB wih the supply voltage is 1.8v and the drain current is 8mA.

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Design of 3.1-10.6GHz CMOS LNA Based on Input Matching Technique of Common-Gate Topology

Applied Mechanics and Materials ◽

10.4028/www.scientific.net/amm.479-480.1014 ◽

2013 ◽

Vol 479-480 ◽

pp. 1014-1017

Author(s):

Yi Cheng Chang ◽

Meng Ting Hsu ◽

Yu Chang Hsieh

Keyword(s):

Noise Figure ◽

Supply Voltage ◽

Average Power ◽

Wide Band ◽

Low Noise ◽

Input Matching ◽

Common Gate ◽

Cmos Lna ◽

Noise Amplifier ◽

Is Design

In this study, three stage ultra-wide-band CMOS low-noise amplifier (LNA) is presented. The UWB LNA is design in 0.18μm TSMC CMOS technique. The LNA input and output return loss are both less than-10dB, and achieved 10dB of average power gain, the minimum noise figure is 6.55dB, IIP3 is about-9.5dBm. It consumes 11mW from a 1.0-V supply voltage.

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A 219-µW ultra-low power low-noise amplifier for IEEE 802.15.4 based battery powered, portable, wearable IoT applications

SN Applied Sciences ◽

10.1007/s42452-021-04402-0 ◽

2021 ◽

Vol 3 (4) ◽

Author(s):

S. Chrisben Gladson ◽

Adith Hari Narayana ◽

V. Thenmozhi ◽

M. Bhaskar

Keyword(s):

Low Power ◽

Ieee 802.15.4 ◽

Low Voltage ◽

Low Noise ◽

Low Noise Amplifier ◽

Cmos Process ◽

Process Technology ◽

Ultra Low Power ◽

Power Mode ◽

Noise Amplifier

AbstractDue to the increased processing data rates, which is required in applications such as fifth-generation (5G) wireless networks, the battery power will discharge rapidly. Hence, there is a need for the design of novel circuit topologies to cater the demand of ultra-low voltage and low power operation. In this paper, a low-noise amplifier (LNA) operating at ultra-low voltage is proposed to address the demands of battery-powered communication devices. The LNA dual shunt peaking and has two modes of operation. In low-power mode (Mode-I), the LNA achieves a high gain ($$S21$$ S 21 ) of 18.87 dB, minimum noise figure ($${NF}_{min.}$$ NF m i n . ) of 2.5 dB in the − 3 dB frequency range of 2.3–2.9 GHz, and third-order intercept point (IIP3) of − 7.9dBm when operating at 0.6 V supply. In high-power mode (Mode-II), the achieved gain, NF, and IIP3 are 21.36 dB, 2.3 dB, and 13.78dBm respectively when operating at 1 V supply. The proposed LNA is implemented in UMC 180 nm CMOS process technology with a core area of $$0.40{\mathrm{ mm}}^{2}$$ 0.40 mm 2 and the post-layout validation is performed using Cadence SpectreRF circuit simulator.

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