Design of a Capacitor Cross-Coupled Common Gate Wideband Low Noise Amplifier with Noise Canceling Technique

2014 ◽  
Vol 618 ◽  
pp. 548-552
Author(s):  
Dan Song ◽  
Xiang Ning Fan ◽  
Kuan Bao ◽  
Zai Jun Hua
Keyword(s):  
Noise Figure ◽  
Supply Voltage ◽  
Drain Current ◽  
Low Noise ◽  
Low Noise Amplifier ◽  
Noise Characteristic ◽  
Cmos Process ◽  
Common Gate ◽  
Noise Amplifier ◽  
Noise Canceling

This paper presents a wideband low noise amplifier (LNA) for multi-standard radio application .The low noise amplifier achieves wideband matching with the structure of differential common gate .Meanwhile ,the low noise characteristic is achieved by noise canceling and capacitor cross-coupled. Fabricated in 0.18μm CMOS process, the LNA is designed to operate from 700MHz to 2.6GHz.As are shown in the results of simulation, when the LNA operates from 700MHz to 2.6GHz,the S11 is less than-10dB,the gain achieves 8.5 dB and the variation is within ±0.5dB.The noise figure is 2.2dB wih the supply voltage is 1.8v and the drain current is 8mA.

A 1.4mW 900MHz LNA with Noise-Canceling Technique in 130nm CMOS Process

2017 ◽  
Vol 27 (01) ◽  
pp. 1850003 ◽  
Author(s):  
Shaomin Huang ◽  
Zhongpan Yang ◽  
Chao Hua
Keyword(s):  
Power Dissipation ◽  
Noise Figure ◽  
Supply Voltage ◽  
Low Noise ◽  
Common Source ◽  
Cmos Process ◽  
Measurement Results ◽  
Common Gate ◽  
Noise Amplifier ◽  
Noise Canceling

A noise-canceling low noise amplifier (LNA) structure is proposed in this paper. The LNA works in the 900[Formula: see text]MHz ISM band. The techniques of noise canceling and current-reusing are proposed to improve the noise performance and reduce the power dissipation. The noise cancellation schema is realized by mutually canceling the noise currents of the common-source and common-gate amplifiers. A prototype of the LNA is designed and fabricated in a standard 130[Formula: see text]nm CMOS process. Measurement results under a 1.2[Formula: see text]V supply voltage show that the proposed LNA achieves a voltage gain of 18[Formula: see text]dB and a noise figure of 2[Formula: see text]dB. The whole circuit only consumes a power dissipation of 1.4[Formula: see text]mW.

Optimized Design of Low Power Complementary Metal Oxide Semiconductor Low Noise Amplifier for Zigbee Application

2021 ◽  
Vol 18 (4) ◽  
pp. 1327-1330
Author(s):  
S. Manjula ◽  
R. Karthikeyan ◽  
S. Karthick ◽  
N. Logesh ◽  
M. Logeshkumar
Keyword(s):  
Low Power ◽  
Noise Figure ◽  
Supply Voltage ◽  
Low Noise ◽  
Low Noise Amplifier ◽  
Oxide Semiconductor ◽  
Design System ◽  
Cmos Process ◽  
Design Specifications ◽  
Noise Amplifier

An optimized high gain low power low noise amplifier (LNA) is presented using 90 nm CMOS process at 2.4 GHz frequency for Zigbee applications. For achieving desired design specifications, the LNA is optimized by particle swarm optimization (PSO). The PSO is successfully implemented for optimizing noise figure (NF) when satisfying all the design specifications such as gain, power dissipation, linearity and stability. PSO algorithm is developed in MATLAB to optimize the LNA parameters. The LNA with optimized parameters is simulated using Advanced Design System (ADS) Simulator. The LNA with optimized parameters produces 21.470 dB of voltage gain, 1.031 dB of noise figure at 1.02 mW power consumption with 1.2 V supply voltage. The comparison of designed LNA with and without PSO proves that the optimization improves the LNA results while satisfying all the design constraints.

A 1.2 V CMOS COMMON-GATE LOW NOISE AMPLIFIER FOR UWB WIRELESS COMMUNICATIONS

2013 ◽  
Vol 22 (07) ◽  
pp. 1350052 ◽  
Author(s):  
HOSEIN ALAVI-RAD ◽  
SOHEYL ZIABAKHSH ◽  
MUSTAPHA C. E. YAGOUB
Keyword(s):  
Reflection Coefficient ◽  
Noise Figure ◽  
Supply Voltage ◽  
Wide Band ◽  
Low Noise ◽  
Low Noise Amplifier ◽  
Ultra Wide Band ◽  
Band Frequency ◽  
Common Gate ◽  
Noise Amplifier

In this paper, an ultra-wide band 0.18 μm CMOS common-gate low-noise amplifier (LNA) is presented. Designed in the ultra-wide band frequency range of 3.1–10.6 GHz, it uses a current-reused technique with modified input matching. This approach allowed obtaining a flat broadband gain of 12.75 ± 0.83 dB with an input reflection coefficient less than -5.5 dB, an output reflection coefficient less than -7 dB, and a noise figure less than 3.7 dB. Furthermore, the proposed low-power LNA consumes only 12.14 mW (excluding buffer) from a 1.2 V supply voltage.

Wideband Input Matching CMOS Low-Noise Amplifier with Noise and Distortion Cancellation

2019 ◽  
Vol 29 (04) ◽  
pp. 2050059
Author(s):  
Asieh Parhizkar Tarighat ◽  
Mostafa Yargholi
Keyword(s):  
Noise Figure ◽  
Supply Voltage ◽  
Low Noise ◽  
Low Noise Amplifier ◽  
Cmos Process ◽  
Modified Technique ◽  
Input Matching ◽  
Noise Cancelling ◽  
Resistive Feedback ◽  
Noise Amplifier

In this paper, a wideband low-noise amplifier (LNA) is designed based on the resistive feedback topology with a TSMC 0.18[Formula: see text][Formula: see text]m standard RF CMOS process. Bandwidth expansion is provided by the second-order Chebyshev filter. The noise figure (NF) increases at high frequency because of the source parasitic capacitors of the cascode transistor; so, noise cancelling technique is applied to the cascode transistor of the proposed LNA. Bias conditions and sizes of the transistors are optimized to cancel the nonlinear transconductance ([Formula: see text]). With this modified technique, low noise figure, high linearity and improved input and output matching can be attained for 3.1–10.6[Formula: see text]GHz frequency band. Post-layout simulation result of the proposed LNA shows the maximum power gain of 17[Formula: see text]dB at 5.5[Formula: see text]GHz frequency, NF of lower than 4.5[Formula: see text]dB over the whole band of 3.1–10.6[Formula: see text]GHz, maximum IIP2 of [Formula: see text]28[Formula: see text]dBm and IIP3 of [Formula: see text]7.5[Formula: see text]dBm, while dissipating 9[Formula: see text]mW (with buffer) from a 1.8 V supply voltage. It occupies [Formula: see text]m silicon die area.

Design of 3.1-10.6GHz CMOS LNA Based on Input Matching Technique of Common-Gate Topology

2013 ◽  
Vol 479-480 ◽  
pp. 1014-1017
Author(s):  
Yi Cheng Chang ◽  
Meng Ting Hsu ◽  
Yu Chang Hsieh
Keyword(s):  
Noise Figure ◽  
Supply Voltage ◽  
Average Power ◽  
Wide Band ◽  
Low Noise ◽  
Input Matching ◽  
Common Gate ◽  
Cmos Lna ◽  
Noise Amplifier ◽  
Is Design

In this study, three stage ultra-wide-band CMOS low-noise amplifier (LNA) is presented. The UWB LNA is design in 0.18μm TSMC CMOS technique. The LNA input and output return loss are both less than-10dB, and achieved 10dB of average power gain, the minimum noise figure is 6.55dB, IIP3 is about-9.5dBm. It consumes 11mW from a 1.0-V supply voltage.

scholarly journals A 2.4 GHz low noise amplifier design at 130nm CMOS technology using common gate topology for WiFi / WiMAX application

2017 ◽  
Vol 7 (1.3) ◽  
pp. 69
Author(s):  
M. Ramana Reddy ◽  
N.S Murthy Sharma ◽  
P. Chandra Sekhar
Keyword(s):  
Noise Figure ◽  
Cmos Technology ◽  
Low Noise ◽  
Low Noise Amplifier ◽  
Low Power Consumption ◽  
Common Gate ◽  
Chip Size ◽  
Overall Performance ◽  
Amplifier Design ◽  
Noise Amplifier

The proposed work shows an innovative designing in TSMC 130nm CMOS technology. A 2.4 GHz common gate topology low noise amplifier (LNA) using an active inductor to attain the low power consumption and to get the small chip size in layout design. By using this Common gate topology achieves the noise figure of 4dB, Forward gain (S21) parameter of 14.7dB, and the small chip size of 0.26 mm, while 0.8mW power consuming from a 1.1V in 130nm CMOS gives the better noise figure and improved the overall performance.

STUDY OF PARASITIC CAPACITANCE EFFECT ON NOISE FIGURE OF IDCLNA IN DEEP SUBMICRON CMOS TECHNOLOGIES

2014 ◽  
Vol 23 (05) ◽  
pp. 1450058
Author(s):  
S. MANJULA ◽  
D. SELVATHI
Keyword(s):  
Noise Figure ◽  
High Gain ◽  
Low Noise ◽  
Low Noise Amplifier ◽  
Current Gain ◽  
Cmos Process ◽  
Short Channel ◽  
Trade Offs ◽  
Noise Amplifier ◽  
The Impact

Low noise amplifier (LNA) is an important component in RF receiver front end. An inductively degenerated cascode low noise amplifier (IDCLNA) is mostly preferred for producing good trade-offs such as high gain, low noise figure (NF), high reverse isolation and low power consumption for narrowband applications. This IDCLNA structure is also used to reduce the gate induced noise on the noise performance by inserting the capacitance in parallel with the gate-to-source capacitance of main transistor. Usually, the parasitic overlap capacitances can impose serious constraints on achievable performance and is taken into account in IDCLNA. In this paper, IDCLNA is designed at a frequency of 2.4 GHz with analyzing the impact of parasitic overlap capacitances on IDCLNA in terms of unity current gain frequency (f T ) which will affect the NF of IDCLNA and simulated using 130 nm, 90 nm and 65 nm CMOS technologies. The NF of IDCLNA with and without parasitic overlap capacitances are analyzed and compared for different short channel CMOS processes. Simulation results show that the parasitic overlap capacitances have advantageous to reduce the gate induced noise in IDCLNA for 130-nm CMOS process for 2.4 GHz applications.

A wideband CMOS single-ended low noise amplifier employing negative resistance technique

2018 ◽  
Vol 32 (06) ◽  
pp. 1850068 ◽  
Author(s):  
Benqing Guo ◽  
Hongpeng Chen ◽  
Xuebing Wang ◽  
Jun Chen ◽  
Yueyue Li ◽  
...  
Keyword(s):  
Power Dissipation ◽  
Noise Figure ◽  
Cmos Technology ◽  
Negative Resistance ◽  
Low Noise ◽  
Low Noise Amplifier ◽  
Common Gate ◽  
Noise Amplifier ◽  
Maximal Gain ◽  
Resistance Structure

A wideband common-gate CMOS low noise amplifier with negative resistance technique is proposed. A novel single-ended negative resistance structure is employed to improve gain and noise of the LNA. The inductor resonating is adopted at the input stage and load stage to meet wideband matching and compensate gain roll-off at higher frequencies. Implemented in a 0.18 [Formula: see text]m CMOS technology, the proposed LNA demonstrates in simulations a maximal gain of 16.4 dB across the 3 dB bandwidth of 0.2–3 GHz. The in-band noise figure of 3.4–4.7 dB is obtained while the IIP3 of 5.3–6.8 dBm and IIP2 of 12.5–17.2 dBm are post-simulated in the designed frequency band. The LNA core consumes a power dissipation of 3.8 mW under a 1.5 V power supply.

A FULLY INTEGRATED MULTIBAND CMOS 0.35 μM LNA FOR IEEE802.16 STANDARD

2013 ◽  
Vol 22 (02) ◽  
pp. 1250088 ◽  
Author(s):  
MERIAM BEN AMOR ◽  
MOURAD LOULOU ◽  
SEBASTIEN QUINTANEL ◽  
DANIEL PASQUET
Keyword(s):  
Noise Figure ◽  
Supply Voltage ◽  
Wide Band ◽  
Low Noise ◽  
Cmos Process ◽  
Frequency Range ◽  
Fully Integrated ◽  
Input Matching ◽  
Noise Amplifier ◽  
Chebyshev Filter

In this paper we present the design of a fully integrated low noise amplifier for WiMAX standard with AMS 0.35 μm CMOS process. This LNA is designed to cover the frequency range for licensed and unlicensed bands of the WiMAX 2.3–5.9 GHz. The proposed amplifier achieves a wide band input and output matching with S11 and S22 lower than -10 dB, a flat gain of 12 dB and a noise figure around 3.5 dB for the entire band and from the upper to the higher frequencies. The presented wide band LNA employs a Chebyshev filter for input matching and an inductive shunt feedback for output matching with a bias current of 15 mA and a supply voltage of 2.5 V.

An ESD Protected Wideband CMOS Low Noise Amplifier Employing Active Feedback Technique

2011 ◽  
Vol 403-408 ◽  
pp. 2809-2813
Author(s):  
Kuan Bao ◽  
Xiang Ning Fan
Keyword(s):  
Noise Figure ◽  
Low Noise ◽  
Low Noise Amplifier ◽  
Cmos Process ◽  
Fully Integrated ◽  
Input Matching ◽  
Active Feedback ◽  
Cmos Lna ◽  
Noise Amplifier ◽  
On Chip

This paper presents a wideband low noise amplifier (LNA) for multi-standard radio applications. The low noise characteristic and input matching are simultaneously achieved by active-feedback technique. Bond-wire inductors and electrostatic devices (ESDs) are co-designed to improve the chip performance. Implemented in 0.18-μm CMOS process, the core size of the fully integrated LNA circuits is 535 μm×425 μm without any passive on-chip inductor. The simulated gain and the minimal noise figure of the CMOS LNA are 17.5 dB and 2.0 dB, respectively. The LNA achieves a -3dB bandwidth of 3.1 GHz. And the simulated IIP3 is -4.4 dBm at 2.5 GHz. Operating at 1.8V, the LNA draws a current of 7.7 mA.

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