A FULLY INTEGRATED MULTIBAND CMOS 0.35 μM LNA FOR IEEE802.16 STANDARD

2013 ◽  
Vol 22 (02) ◽  
pp. 1250088 ◽  
Author(s):  
MERIAM BEN AMOR ◽  
MOURAD LOULOU ◽  
SEBASTIEN QUINTANEL ◽  
DANIEL PASQUET
Keyword(s):  
Noise Figure ◽  
Supply Voltage ◽  
Wide Band ◽  
Low Noise ◽  
Cmos Process ◽  
Frequency Range ◽  
Fully Integrated ◽  
Input Matching ◽  
Noise Amplifier ◽  
Chebyshev Filter

In this paper we present the design of a fully integrated low noise amplifier for WiMAX standard with AMS 0.35 μm CMOS process. This LNA is designed to cover the frequency range for licensed and unlicensed bands of the WiMAX 2.3–5.9 GHz. The proposed amplifier achieves a wide band input and output matching with S11 and S22 lower than -10 dB, a flat gain of 12 dB and a noise figure around 3.5 dB for the entire band and from the upper to the higher frequencies. The presented wide band LNA employs a Chebyshev filter for input matching and an inductive shunt feedback for output matching with a bias current of 15 mA and a supply voltage of 2.5 V.

Design of 3.1-10.6GHz CMOS LNA Based on Input Matching Technique of Common-Gate Topology

2013 ◽  
Vol 479-480 ◽  
pp. 1014-1017
Author(s):  
Yi Cheng Chang ◽  
Meng Ting Hsu ◽  
Yu Chang Hsieh
Keyword(s):  
Noise Figure ◽  
Supply Voltage ◽  
Average Power ◽  
Wide Band ◽  
Low Noise ◽  
Input Matching ◽  
Common Gate ◽  
Cmos Lna ◽  
Noise Amplifier ◽  
Is Design

In this study, three stage ultra-wide-band CMOS low-noise amplifier (LNA) is presented. The UWB LNA is design in 0.18μm TSMC CMOS technique. The LNA input and output return loss are both less than-10dB, and achieved 10dB of average power gain, the minimum noise figure is 6.55dB, IIP3 is about-9.5dBm. It consumes 11mW from a 1.0-V supply voltage.

An ESD Protected Wideband CMOS Low Noise Amplifier Employing Active Feedback Technique

2011 ◽  
Vol 403-408 ◽  
pp. 2809-2813
Author(s):  
Kuan Bao ◽  
Xiang Ning Fan
Keyword(s):  
Noise Figure ◽  
Low Noise ◽  
Low Noise Amplifier ◽  
Cmos Process ◽  
Fully Integrated ◽  
Input Matching ◽  
Active Feedback ◽  
Cmos Lna ◽  
Noise Amplifier ◽  
On Chip

This paper presents a wideband low noise amplifier (LNA) for multi-standard radio applications. The low noise characteristic and input matching are simultaneously achieved by active-feedback technique. Bond-wire inductors and electrostatic devices (ESDs) are co-designed to improve the chip performance. Implemented in 0.18-μm CMOS process, the core size of the fully integrated LNA circuits is 535 μm×425 μm without any passive on-chip inductor. The simulated gain and the minimal noise figure of the CMOS LNA are 17.5 dB and 2.0 dB, respectively. The LNA achieves a -3dB bandwidth of 3.1 GHz. And the simulated IIP3 is -4.4 dBm at 2.5 GHz. Operating at 1.8V, the LNA draws a current of 7.7 mA.

Wideband Input Matching CMOS Low-Noise Amplifier with Noise and Distortion Cancellation

2019 ◽  
Vol 29 (04) ◽  
pp. 2050059
Author(s):  
Asieh Parhizkar Tarighat ◽  
Mostafa Yargholi
Keyword(s):  
Noise Figure ◽  
Supply Voltage ◽  
Low Noise ◽  
Low Noise Amplifier ◽  
Cmos Process ◽  
Modified Technique ◽  
Input Matching ◽  
Noise Cancelling ◽  
Resistive Feedback ◽  
Noise Amplifier

In this paper, a wideband low-noise amplifier (LNA) is designed based on the resistive feedback topology with a TSMC 0.18[Formula: see text][Formula: see text]m standard RF CMOS process. Bandwidth expansion is provided by the second-order Chebyshev filter. The noise figure (NF) increases at high frequency because of the source parasitic capacitors of the cascode transistor; so, noise cancelling technique is applied to the cascode transistor of the proposed LNA. Bias conditions and sizes of the transistors are optimized to cancel the nonlinear transconductance ([Formula: see text]). With this modified technique, low noise figure, high linearity and improved input and output matching can be attained for 3.1–10.6[Formula: see text]GHz frequency band. Post-layout simulation result of the proposed LNA shows the maximum power gain of 17[Formula: see text]dB at 5.5[Formula: see text]GHz frequency, NF of lower than 4.5[Formula: see text]dB over the whole band of 3.1–10.6[Formula: see text]GHz, maximum IIP2 of [Formula: see text]28[Formula: see text]dBm and IIP3 of [Formula: see text]7.5[Formula: see text]dBm, while dissipating 9[Formula: see text]mW (with buffer) from a 1.8 V supply voltage. It occupies [Formula: see text]m silicon die area.

Design of Low-Noise Two-Path Amplifier for 6–16 GHz Applications

2020 ◽  
pp. 2150136
Author(s):  
Asieh Parhizkar Tarighat ◽  
Mostafa Yargholi
Keyword(s):  
Noise Figure ◽  
Impedance Matching ◽  
High Gain ◽  
Low Noise ◽  
Cmos Process ◽  
Input Matching ◽  
Inductive Peaking ◽  
Linearity Improvement ◽  
Noise Amplifier ◽  
Path Structure

A two-path low-noise amplifier (LNA) is designed with TSMC 0.18[Formula: see text][Formula: see text]m standard RF CMOS process for 6–16[Formula: see text]GHz frequency band applications. The principle of a conventional resistive shunt feedback LNA is analyzed to demonstrate the trade-off between the noise figure (NF) and the input matching. To alleviate the mentioned issue for wideband application, this structure with noise canceling technique and linearity improvement are applied to a two-path structure. Flat and high gain is supplied by the primary path; while the input and output impedance matching are provided by the secondary path. The [Formula: see text][Formula: see text]dB bandwidth can be increased to a higher frequency by inductive peaking, which is used at the first stage of the two paths. Besides, by biasing the transistors at the threshold voltage, low power dissipation is achieved. The [Formula: see text][Formula: see text]dB gain bandwidth of the proposed LNA is 10[Formula: see text]GHz, while the maximum power gain of 13.1[Formula: see text]dB is attained. With this structure, minimum NF of 4.6[Formula: see text]dB and noise flatness of 1[Formula: see text]dB in the whole bandwidth can be achieved. The input impedance is matched, and S[Formula: see text] is lower than [Formula: see text]10 dB. With the proposed linearized LNA, the average IIP[Formula: see text][Formula: see text]dBm is gained, while it occupies 1051.7[Formula: see text][Formula: see text]m die area.

A 1.8 to 4 GHz inductor-less highly linear CMOS LNA for wire-less receivers

2021 ◽  
pp. 11-20
Author(s):  
Nguyen Huu Tho
Keyword(s):  
Noise Figure ◽  
Impedance Matching ◽  
Wide Band ◽  
Low Noise ◽  
Common Source ◽  
Cmos Process ◽  
Wide Range ◽  
Active Feedback ◽  
Cmos Lna ◽  
Noise Amplifier

This paper presents an inductor-less wide-band highly linear low-noise amplifier (LNA) for wire-less receivers. The inductor-less LNA consists of a complementary current-reuse common source amplifier combined with a low-current active feedback to obtain wide range input impedance matching and low noise figure. In our LNA, a degeneration resistor is utilized to improve linearity of the LNA. Furthermore, we designed a bypass mode for the LNA to extend the range of its applications. The proposed LNA is implemented in 28 nm CMOS process. It has a gain of 14.9 dB and a bandwidth of 2.2 GHz. The noise figure (NF) is 1.95 dB and the third-order input intercept point (IIP3) is 24.8 dBm at 2.3 GHz. It consumes 17.2 mW at a 0.9-V supply and has an area of 0.011 mm2.

Optimized Design of Low Power Complementary Metal Oxide Semiconductor Low Noise Amplifier for Zigbee Application

2021 ◽  
Vol 18 (4) ◽  
pp. 1327-1330
Author(s):  
S. Manjula ◽  
R. Karthikeyan ◽  
S. Karthick ◽  
N. Logesh ◽  
M. Logeshkumar
Keyword(s):  
Low Power ◽  
Noise Figure ◽  
Supply Voltage ◽  
Low Noise ◽  
Low Noise Amplifier ◽  
Oxide Semiconductor ◽  
Design System ◽  
Cmos Process ◽  
Design Specifications ◽  
Noise Amplifier

An optimized high gain low power low noise amplifier (LNA) is presented using 90 nm CMOS process at 2.4 GHz frequency for Zigbee applications. For achieving desired design specifications, the LNA is optimized by particle swarm optimization (PSO). The PSO is successfully implemented for optimizing noise figure (NF) when satisfying all the design specifications such as gain, power dissipation, linearity and stability. PSO algorithm is developed in MATLAB to optimize the LNA parameters. The LNA with optimized parameters is simulated using Advanced Design System (ADS) Simulator. The LNA with optimized parameters produces 21.470 dB of voltage gain, 1.031 dB of noise figure at 1.02 mW power consumption with 1.2 V supply voltage. The comparison of designed LNA with and without PSO proves that the optimization improves the LNA results while satisfying all the design constraints.

A Fully Integrated 5.2-GHz CMOS Variable Gain LNA for 802.11a WLAN

2012 ◽  
Vol 433-440 ◽  
pp. 5579-5583
Author(s):  
Ji Hai Duan ◽  
Chun Lei Kang
Keyword(s):  
Power Supply ◽  
Return Loss ◽  
Noise Figure ◽  
High Gain ◽  
Low Noise ◽  
Cmos Process ◽  
Small Signal ◽  
Fully Integrated ◽  
Variable Gain ◽  
Noise Amplifier

A fully integrated 5.2GHz variable gain low noise amplifier (VGLNA) in a 0.18μm CMOS process is proposed in this paper. The VGLAN can achieve a maximum small signal gain of 17.85 dB within the noise figure (NF) of 2.04 dB and a minimum gain of 2.04 dB with good input return loss. The LNA’s P1dB in the high gain mode is -17.5 dBm. The LAN consumes only 14.58 mW from a 1.8V power supply.

A MULTI-BAND LOW NOISE AMPLIFIER WITH GAIN FLATNESS AND BANDWIDTH ENHANCEMENT

2014 ◽  
Vol 23 (02) ◽  
pp. 1450017 ◽  
Author(s):  
SAN-FU WANG ◽  
JAN-OU WU ◽  
YANG-HSIN FAN ◽  
JHEN-JI WANG
Keyword(s):  
Performance Enhancement ◽  
Supply Voltage ◽  
Low Noise ◽  
Low Noise Amplifier ◽  
Cmos Process ◽  
Bandwidth Enhancement ◽  
Input Matching ◽  
Noise Amplifier ◽  
Tunable Frequency ◽  
Multi Band

In this paper, a differential multi-band CMOS low noise amplifier (LNA) is proposed that is operated within a range of 1500–2700 MHz with input matching capacitor switching and gain flatness performance enhancement technique. Traditional multi-band LNAs have poor performances on gain flatness performance. Therefore, we propose a new multi-band LNA which obtain good gain flatness performance by integrating the characteristics of the transistor trans-conductance and LC resonant load. The new LNA can also achieve a tunable frequency at different matching capacitance conditions. The post-layout simulation results shows that the voltage gain is between 19.3 dB and 22.4 dB, the NF is less than 2.5 dB, and the 1-dB compression point is about -5.1 dBm. The LNA consumes 17.79 mW under 1.8 V supply voltage in TSMC 0.18-um RF CMOS process.

A 1.2 V CMOS COMMON-GATE LOW NOISE AMPLIFIER FOR UWB WIRELESS COMMUNICATIONS

2013 ◽  
Vol 22 (07) ◽  
pp. 1350052 ◽  
Author(s):  
HOSEIN ALAVI-RAD ◽  
SOHEYL ZIABAKHSH ◽  
MUSTAPHA C. E. YAGOUB
Keyword(s):  
Reflection Coefficient ◽  
Noise Figure ◽  
Supply Voltage ◽  
Wide Band ◽  
Low Noise ◽  
Low Noise Amplifier ◽  
Ultra Wide Band ◽  
Band Frequency ◽  
Common Gate ◽  
Noise Amplifier

In this paper, an ultra-wide band 0.18 μm CMOS common-gate low-noise amplifier (LNA) is presented. Designed in the ultra-wide band frequency range of 3.1–10.6 GHz, it uses a current-reused technique with modified input matching. This approach allowed obtaining a flat broadband gain of 12.75 ± 0.83 dB with an input reflection coefficient less than -5.5 dB, an output reflection coefficient less than -7 dB, and a noise figure less than 3.7 dB. Furthermore, the proposed low-power LNA consumes only 12.14 mW (excluding buffer) from a 1.2 V supply voltage.

scholarly journals Ultra-Wide Band LNA Design using Active Inductor with Modified Noise Cancellation Technique

2019 ◽  
Vol 8 (2) ◽  
pp. 2406-2410
Keyword(s):  
Noise Figure ◽  
Supply Voltage ◽  
Wide Band ◽  
Low Noise ◽  
Ultra Wide Band ◽  
Active Inductor ◽  
Cmos Process ◽  
Chip Area ◽  
Chip Size ◽  
Lna Design

An Ultra-Wide Band (UWB) Low Noise Amplifier (LNA) is affective in deciding the chip size and in the implementation cost at Radio Frequency applications. The proposed LNA design with an active inductor is a different solution to trounce the habit of passive inductors to cut the chip area. Designed in 90-nm CMOS process, a voltage gain of 9dB to 15.5dB for a supply voltage of 0.9v to 1.8V with a smallest Noise Figure (NF) of 5.7dB is achieved by the LNA, with low power utilization and at 2.40 GHz, with 345um2 of chip area.

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