Fully Differential Class-AB OTA with Improved CMRR

2017 ◽  
Vol 26 (11) ◽  
pp. 1750169 ◽  
Author(s):  
Francesco Centurelli ◽  
Pietro Monsurrò ◽  
Gaetano Parisi ◽  
Pasquale Tommasino ◽  
Alessandro Trifiletti
Keyword(s):  
Cmos Technology ◽  
Current Mirror ◽  
Differential Mode ◽  
Common Mode ◽  
Common Mode Rejection Ratio ◽  
Class Ab ◽  
Fully Differential ◽  
Rejection Ratio ◽  
Mode Behavior ◽  
The Common

This paper presents a fully differential class-AB current mirror OTA that improves the common-mode behavior of a topology that presents very good differential-mode performance but poor common-mode rejection ratio (CMRR). The proposed solution requires a low-current auxiliary circuit driven by the input signal, to compensate the effect of the common-mode input component. Simulations in 40-nm CMOS technology show a net reduction of common-mode gain of more than 90[Formula: see text]dB without affecting the differential-mode behavior; a sample-and-hold amplifier exploiting the proposed amplifier has also been simulated.

CMRR Analysis of the 3 Op-Amp Instrumentation Amplifier with Noise

2014 ◽  
Vol 488-489 ◽  
pp. 1096-1099
Author(s):  
Tie Feng Wu ◽  
Zhi Chao Zhao ◽  
De Wei Dai ◽  
Shun Ji Piao ◽  
Jing Li
Keyword(s):  
Instrumentation Amplifier ◽  
Weak Signal ◽  
Common Mode ◽  
Common Mode Rejection Ratio ◽  
Application Range ◽  
Op Amp ◽  
Rejection Ratio ◽  
The Common

This paper researches the common mode rejection ratio (CMRR) of 3 op-amp instrumentation amplifier of amplifying weak signal and presents a new calculation modal considering noise, non-ideal amplifiers, matched resistor and application restricted by the factors of affecting CMRR. At last, a instrumentation amplifier was designed and built and its measured and computed results of modal are compared. The results show that this modal presented enhances calculating precision and extends application range of instrumentation amplifier. It is valid and reasonable.

scholarly journals Common Mode Voltage Removal using New Balancing Technique for Extraction of Low Level Differential Signals Embedded in Large Common Mode Voltages

2019 ◽  
Vol 9 (1) ◽  
pp. 5533-5538
Keyword(s):  
Differential Amplifier ◽  
Individual Values ◽  
Common Mode ◽  
Common Mode Rejection Ratio ◽  
Rejection Ratio ◽  
Common Mode Voltage ◽  
Wide Range ◽  
The Common ◽  
Specific Band ◽  
The Individual

The paper proposes a method based on new principle for removal of common mode voltages (CMVs) present in the differential signals # . These CMVs can be reduced nearly to zero without using any components with tight tolerances which is achieved using a new balancing technique. It is proved that the performance of the circuit depends only on the ratios and not on the individual values of the resistors because of which the performance of the circuit is not affected over the wide range of temperature. The circuit based on this principle was designed, constructed, tested and results are reported in this paper. Unlike the conventional techniques which use filters for removal of the common mode signals in specific band of the frequencies, the method reported here removes common mode signals of all known and unknown frequencies. Using this method, it is possible to extract very low values of the differential signals in the range of few microvolts where common mode voltages can be as high as few volts. It is possible to improve the effective common mode rejection ratio (CMRR) of any differential amplifier by a factor of more than 103 to 104 with this method.

scholarly journals A 0.3 V, Rail-to-Rail, Ultralow-Power, Non-Tailed, Body-Driven, Sub-Threshold Amplifier

2021 ◽  
Vol 11 (6) ◽  
pp. 2528 ◽  
Author(s):  
Francesco Centurelli ◽  
Riccardo Della Sala ◽  
Giuseppe Scotti ◽  
Alessandro Trifiletti
Keyword(s):  
Supply Voltage ◽  
Cmos Technology ◽  
Gain Bandwidth ◽  
Common Mode ◽  
Input Stage ◽  
Fully Differential ◽  
Common Mode Voltage ◽  
Rail To Rail ◽  
The Common ◽  
Ultralow Power

A novel, inverter-based, fully differential, body-driven, rail-to-rail, input stage topology is proposed in this paper. The input stage exploits a replica bias control loop to set the common mode current and a common mode feed-forward strategy to set its output common mode voltage. This novel cell is used to build an ultralow voltage (ULV), ultralow-power (ULP), two-stage, unbuffered operational amplifier. A dual path compensation strategy is exploited to improve the frequency response of the circuit. The amplifier has been designed in a commercial 130 nm CMOS technology from STMicroelectronics and is able to operate with a nominal supply voltage of 0.3 V and a power consumption as low as 11.4 nW, while showing about 65 dB gain, a gain bandwidth product around 3.6 kHz with a 50 pF load capacitance and a common mode rejection ratio (CMRR) in excess of 60 dB. Transistor-level simulations show that the proposed circuit outperforms most of the state of the art amplifiers in terms of the main figures of merit. The results of extensive parametric and Monte Carlo simulations have demonstrated the robustness of the proposed circuit to PVT and mismatch variations.

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