Design of Broadband LNA Using Improved Self-Bias Architecture

2019 ◽  
Vol 28 (08) ◽  
pp. 1920005 ◽  
Author(s):  
Tian Qi ◽  
Songbai He
Keyword(s):  
Noise Figure ◽  
Low Noise ◽  
Power Gain ◽  
Matching Networks ◽  
Self Bias ◽  
Measurement Results ◽  
Chip Size ◽  
Simulation Results ◽  
Noise Amplifier ◽  
Ku Band

A broadband low-noise amplifier (LNA) using 0.13 [Formula: see text]m GaAs HEMT technology for Ku-band applications is presented in this paper. By introducing an improved self-bias architecture, the LNA is achieved with low noise figure (NF) and high power gain. Compared with traditional LNA, self-bias architecture can reduce DC supplies to single one, and the improved architecture proposed here also takes part in source matching to reduce the complexity matching networks for broadband applications. To verify, an LNA operating over 12–18-GHz bandwidth is fabricated. The measurement results, for all the 72 chips on the wafer, and their average values are in great accordance with the simulation results, with 25.5–27.5-dB power gain, 1.1–1.8-dB NF, 15–17.5-dBm output power at [Formula: see text] and with a chip size of 2 mm [Formula: see text] 1.5 mm.

A Ku-Band Low Noise Amplifier Based on Transformer

2013 ◽  
Vol 655-657 ◽  
pp. 1550-1554 ◽  
Author(s):  
Yu Lin Wang ◽  
Man Long Her ◽  
Ming Wei Hsu ◽  
Wen Ko
Keyword(s):  
Noise Figure ◽  
Low Noise ◽  
Low Noise Amplifier ◽  
Feedback Network ◽  
Chip Size ◽  
Cmos Lna ◽  
Flat Gain ◽  
Noise Amplifier ◽  
Source Degeneration ◽  
Ku Band

The aim of this paper is to design and implement a low noise amplifier (LNA) based on transformer for a Ku-band application. The proposed CMOS LNA can have an enhanced gain because of the cascade topology, a highly flat gain response because of the RC feedback network, and a wide passband because of the source degeneration structure that effectively suppresses the Miller effect. The Ku-band LNA dissipates 22.175 mW power and achieves the S11 of -10.31 to -6.77 dB, S22 of -18.1 to -37.78 dB, flat S21 of 8.78 to 10.59 dB, and noise figure of 3.96 to 5.33 dB across the 12~18 GHz span. The measured output P1dB is approximately -2 dBm. The chip size including all testing pads is only 0.545 x 0.599 mm2.

scholarly journals A 2.4 GHz low noise amplifier design at 130nm CMOS technology using common gate topology for WiFi / WiMAX application

2017 ◽  
Vol 7 (1.3) ◽  
pp. 69
Author(s):  
M. Ramana Reddy ◽  
N.S Murthy Sharma ◽  
P. Chandra Sekhar
Keyword(s):  
Noise Figure ◽  
Cmos Technology ◽  
Low Noise ◽  
Low Noise Amplifier ◽  
Low Power Consumption ◽  
Common Gate ◽  
Chip Size ◽  
Overall Performance ◽  
Amplifier Design ◽  
Noise Amplifier

The proposed work shows an innovative designing in TSMC 130nm CMOS technology. A 2.4 GHz common gate topology low noise amplifier (LNA) using an active inductor to attain the low power consumption and to get the small chip size in layout design. By using this Common gate topology achieves the noise figure of 4dB, Forward gain (S21) parameter of 14.7dB, and the small chip size of 0.26 mm, while 0.8mW power consuming from a 1.1V in 130nm CMOS gives the better noise figure and improved the overall performance.

Design of a 2-Stage Broadband Low Noise Amplifier Based on the Agilent ADS

2015 ◽  
Vol 719-720 ◽  
pp. 862-868
Author(s):  
Yan Fen Chen ◽  
Fu Hong Zhang
Keyword(s):  
Standing Wave ◽  
High Performance ◽  
Low Noise ◽  
Low Noise Amplifier ◽  
Small Signal ◽  
Power Gain ◽  
Input And Output ◽  
Signal Simulation ◽  
Simulation Results ◽  
Noise Amplifier

The noise coefficient and the power gain of a low noise amplifier affect the whole performance of the receiver. This paper presents the design and simulation of 2-stage low noise amplifier using the MGA633P8 and TQP3M9028’s S parameters to set S2P files. Not only analyze how to insert elements to match a broadband circuit, but also make some optimization by using the Agilent ADS in the case of small signal. Simulation results show that the proposed work implements a high performance of 2-stage low noise amplifier which works at 824 MHZ to 1980 MHZ, the gain is greater than 25 db, the noise coefficient is less than 0.6, input and output standing wave ratio (SWR) are both less than 1.3.

scholarly journals Design And Analysis Of CMOS Low Noise Amplifier Circuit For 5-GHz Cascode and Folded Cascode In 180nm Technology

2018 ◽  
Vol 7 (3) ◽  
pp. 143
Author(s):  
T. Kanthi ◽  
D. Sharath Babu Rao
Keyword(s):  
Noise Figure ◽  
Cmos Technology ◽  
Low Noise ◽  
Low Noise Amplifier ◽  
Common Source ◽  
Power Gain ◽  
Amplifier Circuit ◽  
Folded Cascode ◽  
Noise Amplifier ◽  
5 Ghz

This paper is about Low noise amplifier topologies based on 0.18µm CMOS technology. A common source stage with inductive degeneration, cascode stage and folded cascode stage is designed, simulated and the performance has been analyzed. The LNA’s are designed in 5GHz. The LNA of cascode stage of noise figure (NF) 2.044dB and power gain 4.347 is achieved. The simulations are done in cadence virtuoso spectre RF.

Design and Implementation of a Wideband C-Band LNA

2011 ◽  
Vol 130-134 ◽  
pp. 3272-3275
Author(s):  
Jian Ye Zhang ◽  
Ling Tian ◽  
Wei Hong ◽  
Jia Qi Liu
Keyword(s):  
Noise Figure ◽  
Low Noise ◽  
Broad Bandwidth ◽  
Design And Implementation ◽  
Matching Networks ◽  
Input And Output ◽  
Balanced Structure ◽  
Noise Amplifier ◽  
The Stability ◽  
Better Than

This paper presents the design and implementation of a C-band 6-8 GHz wideband low noise amplifier (LNA). The design is based on balanced structure. The compensated matching networks are designed to obtain gain flatness, two Wilkinson couplers are used to obtain good input and output VSWR, a section of microstrip line is introduced between the source and ground to improve the stability. The measured gain is 12±0.5 dB and noise figure is less than 1.5 dB, the input and output VSWR are better than 1.7. The LNA with broad bandwidth, flat gain, low noise figure and high stability can be used in wideband RF receivers.

scholarly journals Research and Design of X-band Low Noise Amplifier Based on CMOS Process

2021 ◽  
Vol 2108 (1) ◽  
pp. 012102
Author(s):  
Chao Ma ◽  
Hongjiang Wu ◽  
Xudong Lu ◽  
Haitao Sun
Keyword(s):  
Noise Figure ◽  
Low Noise ◽  
Low Noise Amplifier ◽  
Center Frequency ◽  
Cmos Process ◽  
Actual Measurement ◽  
Chip Area ◽  
Chip Size ◽  
Noise Amplifier ◽  
Stage Matching

Abstract Based on CMOS process, a low noise amplifier(LNA) operating at 7.4GHz~11.4GHz was designed. The two-stage differential cascode structure is adopted. Transformer was used to achieve inter-stage matching. Balun was used to achieve input and output matching, which reduces the number of inductors used, effectively reduces the chip size while ensuring good gain and noise figure. The actual measurement results show that the power gain at the center frequency of 9.4GHz is 27dB, the maximum noise figure is less than 3.82dB, the output power 1dB compression point is greater than 8dBm, the chip area is only 0.41mm×0.83mm(excluding PAD).

scholarly journals Development of X-Band Transceiver MMIC’s Using GaN Technology

2019 ◽  
Vol 8 (2) ◽  
pp. 1-9
Author(s):  
O. Memioglu ◽  
O. Kazan ◽  
A. Karakuzulu ◽  
I. Turan ◽  
A. Gundel ◽  
...  
Keyword(s):  
Power Amplifiers ◽  
Noise Figure ◽  
Low Noise ◽  
Low Noise Amplifier ◽  
Rf Power ◽  
Rf Switch ◽  
X Band ◽  
Measurement Results ◽  
Noise Amplifier ◽  
Selection Of

This paper describes X-Band power amplifier (PA), low noise amplifier (LNA) and switches that can be used in transmit/receive modules which are developed with GaN technology. For Transmit chain two 25 W high power amplifiers that are tuned between 8-10 GHz and 10-12 GHz bands are designed. A low noise amplifier with 2 W survivability and less than 2dB noise figure is designed for receive chain Furthermore, an RF switch that is capable of withstanding 25 W RF power is developed for the selection of transmit or receive chains. Measurement results show that both power amplifiers produce 25 W of power. Low noise amplifier has more than 20 dB small signal gain with less than 2 dB noise figure. RF switch has 50 dB of isolation with less than 1 dB insertion loss.

scholarly journals Design And Analysis Of CMOS Low Noise Amplifier Circuit For 5-GHz Cascode and Folded Cascode In 180nm Technology

2018 ◽  
Vol 7 (3) ◽  
pp. 149
Author(s):  
T. Kanthi ◽  
D. Sharath Babu Rao
Keyword(s):  
Noise Figure ◽  
Cmos Technology ◽  
Low Noise ◽  
Low Noise Amplifier ◽  
Common Source ◽  
Power Gain ◽  
Amplifier Circuit ◽  
Folded Cascode ◽  
Noise Amplifier ◽  
5 Ghz

This paper is about Low noise amplifier topologies based on 0.18µm CMOS technology. A common source stage with inductive degeneration, cascode stage and folded cascode stage is designed, simulated and the performance has been analyzed. The LNA’s are designed in 5GHz. The LNA of cascode stage of noise figure (NF) 2.044dB and power gain 4.347 is achieved. The simulations are done in cadence virtuoso spectre RF.

scholarly journals Design, Analysis and Measurement Results of a Fully-Integrated Low-power LNA Presenting Faults

2013 ◽  
Vol 8 (1) ◽  
pp. 32-42
Author(s):  
Paulo M. Moreira e Silva ◽  
Fernando Rangel de Sousa
Keyword(s):  
Power Consumption ◽  
Noise Figure ◽  
Cmos Technology ◽  
Low Noise ◽  
Fully Integrated ◽  
Uncertainty Sources ◽  
Measurement Results ◽  
Noise Amplifier ◽  
A Current ◽  
Measured Input

We present in this paper the analysis, design and measurement results of a low noise amplifier (LNA) operating in the ISM band at 2.45 GHz. The circuit topology adopted was based on a current reuse technique to minimize the power consumption. A prototype was fabricated in a 0.18-μm standard CMOS technology and the measured power consumption was 1.1 mW. The measured input reflection coefficient was below -10 dB and the reverse isolation was higher than 20 dB. The measured insertion gain and noise figure were 5.6 dB and 4.8 dB respectively, with divergences from the simulated values of 5 dB and 2 dB, respectively. To explain these discrepancies, we devised an analysis on the circuit, including sources of uncertainties. Moreover, we characterized a transistor included in the LNA die, that helped to explain part of the disagreements. After including the uncertainty sources, we wereaable to explain a deviation of 3.9 dB in the insertion gain with respect to the simulated result.

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