Improving Compression Ratios for Code-Based Test Pattern Compressions through Column-Wise Reordering Algorithms

2020 ◽  
pp. 2150108
Author(s):  
Minghe Zhang ◽  
Jishun Kuang ◽  
Jing Huang ◽  
Renfa Li
Keyword(s):  
Compression Ratio ◽  
Large Scale ◽  
Test Pattern ◽  
Hadamard Matrix ◽  
Primary Component ◽  
Transmission Time ◽  
Test Set ◽  
Test Application ◽  
Chip Testing ◽  
On Chip

Chip testing is an effective way to reduce the number of defective or faulty chips that reach the market. However, as large-scale test patterns need to be transmitted into a circuit under test during testing, the transmission time dominates the test application time of the chip testing. Therefore, code-based compression methods are widely used in compressing test patterns because of their capability to reduce the transmission time and save storage space significantly. Current code-based compression methods cannot fully apply the inherent characteristics of test patterns yet. To address this problem, this study proposes two-stage test pattern preprocessing algorithms, thereby improving the efficiency of the code-based compression method. First, we propose a column-wise reordering for Hadamard matrix (CRHM) algorithm, which decomposes a test set consisting of test patterns into a primary component set (PCS) and a residual component set (RCS). The PCS inherits some 1s from the original test set (OTS), and other 1s belong to the RCS. As the number of 1s contained in the RCS is less than that in the OTS, the RCS can obtain a higher code-based compression ratio. The PCS can be generated by an on-chip generator, which does not consume transmission time. Second, we propose a novel column-wise reordering for the RCS (CRRCS) algorithm. The CRRCS solves the new location of each column of the RCS one by one in the list to decrease the entropy of the RCS. The entropy denotes the shortest length of the codeword required for the symbol to be encoded. The smaller entropy value refers to a higher compression ratio. For the sorted RCS, more high-frequency symbols can be replaced by shorter codewords. Experimental results based on seven code-based compression methods show that the proposed algorithms can increase the average compression ratio by a total of 19.91%, and the highest average compression ratio reaches 85.04% for ISCAS’89 benchmark circuits.

Enabling Electro-Optical Failure Analysis within Extreme Compression Test Architecture

2016 ◽  
Author(s):  
Rudolf Schlangen ◽  
Jon Colburn ◽  
Joe Sarmiento ◽  
Bala Tarun Nelapatla ◽  
Puneet Gupta
Keyword(s):  
Failure Analysis ◽  
Compression Test ◽  
Test Pattern ◽  
Pattern Generation ◽  
Output Data ◽  
Test Compression ◽  
Test Loop ◽  
On Chip ◽  
Test Architecture

Abstract Driven by the need for higher test-compression, increasingly many chip-makers are adopting new DFT architectures such as “Extreme-Compression” (XTR, supported by Synopsys) with on-chip pattern generation and MISR based compression of chain output data. This paper discusses test-loop requirements in general and gives Advantest 93k specific guidelines on test-pattern release and ATE setup necessary to enable the most established EFA techniques such as LVP and SDL (aka DLS, LADA) within the XTR test architecture.

scholarly journals Enhancement of Detecting Permanent Water and Temporary Water in Flood Disasters by Fusing Sentinel-1 and Sentinel-2 Imagery Using Deep Learning Algorithms: Demonstration of Sen1Floods11 Benchmark Datasets

2021 ◽  
Vol 13 (11) ◽  
pp. 2220
Author(s):  
Yanbing Bai ◽  
Wenqi Wu ◽  
Zhengxin Yang ◽  
Jinze Yu ◽  
Bo Zhao ◽  
...  
Keyword(s):  
Remote Sensing ◽  
Deep Learning ◽  
Large Scale ◽  
Learning Algorithms ◽  
Flood Events ◽  
Test Set ◽  
Source Data ◽  
Flood Disasters ◽  
Temporary Water ◽  
Sentinel 2

Identifying permanent water and temporary water in flood disasters efficiently has mainly relied on change detection method from multi-temporal remote sensing imageries, but estimating the water type in flood disaster events from only post-flood remote sensing imageries still remains challenging. Research progress in recent years has demonstrated the excellent potential of multi-source data fusion and deep learning algorithms in improving flood detection, while this field has only been studied initially due to the lack of large-scale labelled remote sensing images of flood events. Here, we present new deep learning algorithms and a multi-source data fusion driven flood inundation mapping approach by leveraging a large-scale publicly available Sen1Flood11 dataset consisting of roughly 4831 labelled Sentinel-1 SAR and Sentinel-2 optical imagery gathered from flood events worldwide in recent years. Specifically, we proposed an automatic segmentation method for surface water, permanent water, and temporary water identification, and all tasks share the same convolutional neural network architecture. We utilize focal loss to deal with the class (water/non-water) imbalance problem. Thorough ablation experiments and analysis confirmed the effectiveness of various proposed designs. In comparison experiments, the method proposed in this paper is superior to other classical models. Our model achieves a mean Intersection over Union (mIoU) of 52.99%, Intersection over Union (IoU) of 52.30%, and Overall Accuracy (OA) of 92.81% on the Sen1Flood11 test set. On the Sen1Flood11 Bolivia test set, our model also achieves very high mIoU (47.88%), IoU (76.74%), and OA (95.59%) and shows good generalization ability.

scholarly journals A Stochastic Model to Describe the Scattering in the Response of Polysilicon MEMS

2021 ◽  
Vol 2 (1) ◽  
pp. 95
Author(s):  
Luca Dassi ◽  
Marco Merola ◽  
Eleonora Riva ◽  
Angelo Santalucia ◽  
Andrea Venturelli ◽  
...  
Keyword(s):  
Silicon Film ◽  
Micro Fabrication ◽  
Micro Electro Mechanical Systems ◽  
Local Fluctuations ◽  
Stochastic Framework ◽  
On Line ◽  
Chip Testing ◽  
On Chip ◽  
Time Required ◽  
Polycrystalline Silicon Film

The current miniaturization trend in the market of inertial microsystems is leading to movable device parts with sizes comparable to the characteristic length-scale of the polycrystalline silicon film morphology. The relevant output of micro electro-mechanical systems (MEMS) is thus more and more affected by a scattering, induced by features resulting from the micro-fabrication process. We recently proposed an on-chip testing device, specifically designed to enhance the aforementioned scattering in compliance with fabrication constraints. We proved that the experimentally measured scattering cannot be described by allowing only for the morphology-affected mechanical properties of the silicon films, and etch defects must be properly accounted for too. In this work, we discuss a fully stochastic framework allowing for the local fluctuations of the stiffness and of the etch-affected geometry of the silicon film. The provided semi-analytical solution is shown to catch efficiently the measured scattering in the C-V plots collected through the test structure. This approach opens up the possibility to learn on-line specific features of the devices, and to reduce the time required for their calibration.

scholarly journals Nanolaser-based emulators of spin Hamiltonians

Nanophotonics ◽  
2020 ◽  
Vol 9 (13) ◽  
pp. 4193-4198 ◽  
Author(s):  
Midya Parto ◽  
William E. Hayenga ◽  
Alireza Marandi ◽  
Demetrios N. Christodoulides ◽  
Mercedeh Khajavikhan
Keyword(s):  
Large Scale ◽  
Optimization Problems ◽  
Exchange Interactions ◽  
Np Hard ◽  
Spin Models ◽  
Geometric Frustration ◽  
Spin Hamiltonians ◽  
Hard Problems ◽  
On Chip ◽  
Classical Spin Models

AbstractFinding the solution to a large category of optimization problems, known as the NP-hard class, requires an exponentially increasing solution time using conventional computers. Lately, there has been intense efforts to develop alternative computational methods capable of addressing such tasks. In this regard, spin Hamiltonians, which originally arose in describing exchange interactions in magnetic materials, have recently been pursued as a powerful computational tool. Along these lines, it has been shown that solving NP-hard problems can be effectively mapped into finding the ground state of certain types of classical spin models. Here, we show that arrays of metallic nanolasers provide an ultra-compact, on-chip platform capable of implementing spin models, including the classical Ising and XY Hamiltonians. Various regimes of behavior including ferromagnetic, antiferromagnetic, as well as geometric frustration are observed in these structures. Our work paves the way towards nanoscale spin-emulators that enable efficient modeling of large-scale complex networks.

scholarly journals Simba

2021 ◽  
Vol 64 (6) ◽  
pp. 107-116
Author(s):  
Yakun Sophia Shao ◽  
Jason Cemons ◽  
Rangharajan Venkatesan ◽  
Brian Zimmer ◽  
Matthew Fojtik ◽  
...  
Keyword(s):  
Deep Learning ◽  
Large Scale ◽  
Data Locality ◽  
Coarse Grained ◽  
Batch Size ◽  
Peak Performance ◽  
Large Scale Systems ◽  
High Area ◽  
On Chip ◽  
And Storage

Package-level integration using multi-chip-modules (MCMs) is a promising approach for building large-scale systems. Compared to a large monolithic die, an MCM combines many smaller chiplets into a larger system, substantially reducing fabrication and design costs. Current MCMs typically only contain a handful of coarse-grained large chiplets due to the high area, performance, and energy overheads associated with inter-chiplet communication. This work investigates and quantifies the costs and benefits of using MCMs with finegrained chiplets for deep learning inference, an application domain with large compute and on-chip storage requirements. To evaluate the approach, we architected, implemented, fabricated, and tested Simba, a 36-chiplet prototype MCM system for deep-learning inference. Each chiplet achieves 4 TOPS peak performance, and the 36-chiplet MCM package achieves up to 128 TOPS and up to 6.1 TOPS/W. The MCM is configurable to support a flexible mapping of DNN layers to the distributed compute and storage units. To mitigate inter-chiplet communication overheads, we introduce three tiling optimizations that improve data locality. These optimizations achieve up to 16% speedup compared to the baseline layer mapping. Our evaluation shows that Simba can process 1988 images/s running ResNet-50 with a batch size of one, delivering an inference latency of 0.50 ms.

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