STUDY OF DUAL-MATERIAL GATE (DMG) FinFET USING THREE-DIMENSIONAL NUMERICAL SIMULATION

2006 ◽  
Vol 05 (04n05) ◽  
pp. 541-545 ◽  
Author(s):  
DNAYNESH S. HAVALDAR ◽  
AMITAVA DASGUPTA ◽  
NANDITA DASGUPTA
Keyword(s):  
Carrier Transport ◽  
Three Dimensional ◽  
The Novel ◽  
Short Channel Effects ◽  
Short Channel ◽  
Transport Efficiency ◽  
Channel Effects ◽  
Dual Material ◽  
Single Material ◽  
Numerical Simulator

In this work, the novel characteristics of a FinFET with dual-material gate (DMG) are explored theoretically using a 3D numerical simulator and compared with those of a single material gate (SMG) FinFET in terms of threshold voltage roll off, drain induced barrier lowering (DIBL) and the ratio of transconductance (gm) to drain conductance (gd). Our studies show that the DMG structure achieves simultaneous suppression of short channel effects (SCEs), enhancement in carrier transport efficiency and transconductance. Also, these features can be controlled by engineering the work function and length of gate material.

scholarly journals Π-Shape Silicon Window for Controlling OFF-Current in Junctionless SOI MOSFET

2021 ◽  
Author(s):  
Mahsa Mehrad ◽  
Meysam Zareiee
Keyword(s):  
The Body ◽  
Maximum Temperature ◽  
The Novel ◽  
Short Channel Effects ◽  
Short Channel ◽  
Soi Mosfet ◽  
Buried Oxide ◽  
Novel Structure ◽  
Channel Effects ◽  
Channel Region

Abstract in this paper a modified junctionless transistor is proposed. The aim of the novel structure is controlling off-current using π-shape silicon window in the buried oxide under the source and the channel regions. The π-shape window changes the potential profile in the channel region in which the conduction band energy get away from the body Fermi energy and rebuild an electrostatic potential. Beside the significant reduced off-current, on current has acceptable value in the novel Silicon Region Junctionless MOSFET (SR-JMOSFET) than Conventional Junctionless MOSFET (C-JMOSFET). Moreover, replacing silicon material instead of silicon dioxide in the buried oxide causes reduced maximum temperature in the channel region. In this situation the heat could transfer to the π-shape silicon window and the temperature reduces in the active region, significantly.The simulation with the two-dimensional ATLAS simulator shows that short channel effects such as subthreshold and DIBL are controlled effectively in the SR-JMOSFET. Also, the optimum values of length and thickness of the π-shape window are defined to obtain the best behavior of the device.

Investigation of Short Channel Effects (SCEs) and Analog/RF Figure of Merits (FOMs) of Dual-Material Bottom-Spacer Ground-Plane (DMBSGP) FinFET

Silicon ◽  
2019 ◽  
Vol 12 (10) ◽  
pp. 2283-2291 ◽  
Author(s):  
Vadthiya Narendar ◽  
Pallavi Narware ◽  
V. Bheemudu ◽  
Bhukya Sunitha
Keyword(s):  
Ground Plane ◽  
Short Channel Effects ◽  
Short Channel ◽  
Channel Effects ◽  
Dual Material

scholarly journals A compact model of transconductance and drain conductance for DMG-GC-DOT cylindrical gate MOSFET

2020 ◽  
Vol 9 (1) ◽  
pp. 34
Author(s):  
Hind Jaafar ◽  
Abdellah Aouaj ◽  
Benjamin Iñiguez
Keyword(s):  
Compact Model ◽  
Short Channel Effects ◽  
Short Channel ◽  
The Core ◽  
Proposed Model ◽  
Channel Effects ◽  
Design Effectiveness ◽  
Silvaco Atlas ◽  
Dual Material ◽  
Drain Conductance

A compact model for dual-material gate graded-channel and dual-oxide<br />thickness with two dielectric constant different cylindrical gate (DMG-GC-<br />DOTTDCD) MOSFET was investigated in terms of transconductance, drain<br />conductance and capacitance. Short channel effects are modeled with simple<br />expressions, and incorporated into the core of the model (at the drain<br />current). The design effectiveness of DMG-GC-DOTTDCD was monitored<br />in comparing with the DMG-GC-DOT transistor, the effect of variations of<br />technology parameters, was presented in terms of gate polarization and drain<br />polarization. The results indicate that the DMG-GC-DOTTDCD devices<br />have characteristics higher than the DMG-GC-DOT MOSFET. To validate<br />the proposed model, we used the results obtained from the simulation of the<br />device with the SILVACO-ATLAS-TCAD software.

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