New Planar Two-Mode Channel Field-Effect Transistor Suitable for L-Band Microwave Monolithic Integrated Circuits with RF Transmission and Reception Blocks Operating atVdd≤2V

1995 ◽  
Vol 34 (Part 1, No. 2B) ◽  
pp. 1168-1171
Author(s):  
Minoru Sawada ◽  
Emi Fujii ◽  
Shigeharu Matsushita ◽  
Satoshi Terada ◽  
Daijiro Inoue ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
Field Effect ◽  
Field Effect Transistor ◽  
Monolithic Integrated Circuits ◽  
Microwave Monolithic Integrated Circuits ◽  
Effect Transistor ◽  
L Band ◽  
Rf Transmission

Fabrication of SiC JFET-Based Monolithic Integrated Circuits

2010 ◽  
Vol 645-648 ◽  
pp. 1115-1118 ◽  
Author(s):  
Xiao An Fu ◽  
Amita Patil ◽  
Te Hao Lee ◽  
Steven Garverick ◽  
Mehran Mehregany
Keyword(s):  
Integrated Circuits ◽  
Threshold Voltage ◽  
Field Effect ◽  
Field Effect Transistor ◽  
Analog Integrated Circuits ◽  
Single Stage ◽  
Differential Amplifier ◽  
Interlayer Dielectric ◽  
Monolithic Integrated Circuits ◽  
Effect Transistor

We report fabrication of lateral, n-channel, depletion-mode, junction-field-effect-transistor (JFET) monolithic analog integrated circuits (ICs) in 6H-SiC. Ti/TaSi2/Pt forms the contact metalization, Ti/Pt the interconnect metal, and the SiO2/Si3N4/SiO2 interlayer dielectric. The threshold voltage and pinch off current indicate that the actual channel doping and thickness is close to the nominal values specified. The wafer yield for good circuits of a single-stage differential amplifier is 54% out of 46 copies.

scholarly journals A Study on the Effect of the Structural Parameters and Internal Mechanism of a Bilateral Gate-Controlled S/D Symmetric and Interchangeable Bidirectional Tunnel Field Effect Transistor

2021 ◽  
Vol 16 (1) ◽  
Author(s):  
Xiaoshi Jin ◽  
Yicheng Wang ◽  
Kailu Ma ◽  
Meile Wu ◽  
Xi Liu ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
Field Effect ◽  
Field Effect Transistor ◽  
Structural Parameters ◽  
Cmos Integrated Circuits ◽  
Region Length ◽  
Internal Mechanism ◽  
Effect Transistor ◽  
Tunnel Field Effect Transistor ◽  
Switching Characteristics

AbstractA bilateral gate-controlled S/D symmetric and interchangeable bidirectional tunnel field effect transistor (B-TFET) is proposed in this paper, which shows the advantage of bidirectional switching characteristics and compatibility with CMOS integrated circuits compared to the conventional asymmetrical TFET. The effects of the structural parameters, e.g., the doping concentrations of the N+ region and P+ region, length of the N+ region and length of the intrinsic region, on the device performances, e.g., the transfer characteristics, Ion–Ioff ratio and subthreshold swing, and the internal mechanism are discussed and explained in detail.

Prolonged 500°C Operation of 100+ Transistor Silicon Carbide Integrated Circuits

2018 ◽  
Vol 924 ◽  
pp. 949-952 ◽  
Author(s):  
David J. Spry ◽  
Philip G. Neudeck ◽  
Dorothy Lukco ◽  
Liang Yu Chen ◽  
Michael J. Krasowski ◽  
...  
Keyword(s):  
Silicon Carbide ◽  
Integrated Circuits ◽  
Field Effect ◽  
Field Effect Transistor ◽  
Earth Atmosphere ◽  
Surface Atmosphere ◽  
Effect Transistor ◽  
Output Characteristics ◽  
Technology Demonstrator

This report describes more than 5000 hours of successful 500 °C operation of semiconductor integrated circuits (ICs) with more than 100 transistors. Multiple packaged chips with two different 4H-SiC junction field effect transistor (JFET) technology demonstrator circuits have surpassed thousands of hours of oven-testing at 500 °C. After 100 hours of 500 °C burn-in, the circuits (except for 2 failures) exhibit less than 10% change in output characteristics for the remainder of 500 °C testing. We also describe the observation of important differences in IC materials durability when subjected to the first nine constituents of Venus-surface atmosphere at 9.4 MPa and 460 °C in comparison to what is observed for Earth-atmosphere oven testing at 500 °C.

scholarly journals Evidence of Processing Non-Idealities in 4H-SiC Integrated Circuits Fabricated with Two Levels of Metal Interconnect

2016 ◽  
Vol 858 ◽  
pp. 1112-1116 ◽  
Author(s):  
David J. Spry ◽  
Philip G. Neudeck ◽  
Liang Yu Chen ◽  
Laura J. Evans ◽  
Dorothy Lukco ◽  
...  
Keyword(s):  
Conference Proceedings ◽  
Integrated Circuits ◽  
Field Effect ◽  
Field Effect Transistor ◽  
Failure Mechanisms ◽  
Operating Time ◽  
Test Conditions ◽  
Effect Transistor ◽  
Physical Degradation

The fabrication and prolonged 500 °C electrical testing of 4H-SiC junction field effect transistor (JFET) integrated circuits (ICs) with two levels of metal interconnect is reported in another submission to this conference proceedings. While some circuits functioned more than 3000 hours at 500 °C, the majority of packaged ICs from this wafer electrically failed after less than 200 hours of operation in the same test conditions. This work examines the root physical degradation and failure mechanisms believed responsible for observed large discrepancies in 500 °C operating time. Evidence is presented for four distinct issues that significantly impacted 500 °C IC operational yield and lifetime for this wafer.

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