High Performance Cell Transistor for Long Data Retention Time in Giga-bit Density Dynamic Random Access Memory and Beyond

2002 ◽  
Vol 41 (Part 1, No. 12) ◽  
pp. 7276-7281
Author(s):  
Hyung Soo Uh ◽  
Jae-Kyu Lee ◽  
Kinam Kim
Keyword(s):  
Retention Time ◽  
High Performance ◽  
Random Access ◽  
Random Access Memory ◽  
Dynamic Random Access Memory ◽  
Data Retention ◽  
Access Memory ◽  
Density Dynamic

scholarly journals Self-Compliance and High Performance Pt/HfOx/Ti RRAM Achieved through Annealing

Nanomaterials ◽  
2020 ◽  
Vol 10 (3) ◽  
pp. 457 ◽  
Author(s):  
Lei Wu ◽  
Hongxia Liu ◽  
Jinfu Lin ◽  
Shulong Wang
Keyword(s):  
Thermal Annealing ◽  
High Performance ◽  
Electrical Characteristic ◽  
Random Access ◽  
Random Access Memory ◽  
Resistive Random Access Memory ◽  
Data Retention ◽  
Access Memory ◽  
Before And After ◽  
Retention Characteristics

A self-compliance resistive random access memory (RRAM) achieved through thermal annealing of a Pt/HfOx/Ti structure. The electrical characteristic measurements show that the forming voltage of the device annealing at 500 °C decreased, and the switching ratio and uniformity improved. Tests on the device’s cycling endurance and data retention characteristics found that the device had over 1000 erase/write endurance and over 105 s of lifetime (85 °C). The switching mechanisms of the devices before and after annealing were also discussed.

A New Approach for Screening Retention Time Failure Bits in DRAM Device

2013 ◽  
Author(s):  
Bonggu Sung ◽  
Daejung Kim ◽  
Yongjik Park ◽  
Joo-Sun Choi
Keyword(s):  
Retention Time ◽  
Random Access ◽  
Random Access Memory ◽  
Cell Plate ◽  
Dynamic Random Access Memory ◽  
Access Memory ◽  
New Approach ◽  
Root Cause ◽  
Storage Node ◽  
Node Voltage

Abstract In this paper, we investigate that Gate-Induced Drain Leakage (GIDL)-weak cells can be screened effectively by modulation of cell-plate voltage (VPlate) during retention time in dynamic random access memory (DRAM) with Negative Wordline bias scheme (NWL). Boosting storage-node voltage (VSP) by increase of VPlate is the root cause of generating additional GIDL fail bits.

Statistical modeling of dynamic random access memory data retention characteristics

1996 ◽  
Vol 80 (5) ◽  
pp. 3091-3099 ◽  
Author(s):  
A. Hiraiwa ◽  
M. Ogasawara ◽  
N. Natsuaki ◽  
Y. Itoh ◽  
H. Iwai
Keyword(s):  
Statistical Modeling ◽  
Random Access ◽  
Random Access Memory ◽  
Dynamic Random Access Memory ◽  
Data Retention ◽  
Access Memory ◽  
Retention Characteristics
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