scholarly journals Systems-on-Chip with Strong Ordering

2021 ◽  
Vol 18 (1) ◽  
pp. 1-27
Author(s):  
Sooraj Puthoor ◽  
Mikko H. Lipasti
Keyword(s):  
High Performance ◽  
Geometric Mean ◽  
Memory Consistency ◽  
Memory Hierarchies ◽  
Data Parallel ◽  
Consistency Model ◽  
Heterogeneous Processing ◽  
Systems On Chip ◽  
Memory Consistency Model ◽  
On Chip

Sequential consistency (SC) is the most intuitive memory consistency model and the easiest for programmers and hardware designers to reason about. However, the strict memory ordering restrictions imposed by SC make it less attractive from a performance standpoint. Additionally, prior high-performance SC implementations required complex hardware structures to support speculation and recovery. In this article, we introduce the lockstep SC consistency model (LSC), a new memory model based on SC but carefully defined to accommodate the data parallel lockstep execution paradigm of GPUs. We also describe an efficient LSC implementation for an APU system-on-chip (SoC) and show that our implementation performs close to the baseline relaxed model. Evaluation of our implementation shows that the geometric mean performance cost for lockstep SC is just 0.76% for GPU execution and 6.11% for the entire APU SoC compared to a baseline with a weaker memory consistency model. Adoption of LSC in future APU and SoC designs will reduce the burden on programmers trying to write correct parallel programs, while also simplifying the implementation and verification of systems with heterogeneous processing elements and complex memory hierarchies. 1

МЕТОДЫ ДОСТИЖЕНИЯ МАКСИМАЛЬНОЙ ЭФФЕКТИВНОСТИ ПЛАТФОРМЫ ПРОТОТИПИРОВАНИЯ ВЫСОКОПРОИЗВОДИТЕЛЬНЫХ СИСТЕМ НА КРИСТАЛЛЕ НА ЗАДАЧАХ ИСКУССТВЕННОГО ИНТЕЛЛЕКТА

2020 ◽  
Vol 96 (3s) ◽  
pp. 585-588
Author(s):  
С.Е. Фролова ◽  
Е.С. Янакова
Keyword(s):  
Neural Network ◽  
Artificial Intelligence ◽  
Computer Vision ◽  
High Performance ◽  
Systems On Chip ◽  
High Performance Systems ◽  
On Chip ◽  
Network Technologies ◽  
Neural Network Technologies

Предлагаются методы построения платформ прототипирования высокопроизводительных систем на кристалле для задач искусственного интеллекта. Изложены требования к платформам подобного класса и принципы изменения проекта СнК для имплементации в прототип. Рассматриваются методы отладки проектов на платформе прототипирования. Приведены результаты работ алгоритмов компьютерного зрения с использованием нейросетевых технологий на FPGA-прототипе семантических ядер ELcore. Methods have been proposed for building prototyping platforms for high-performance systems-on-chip for artificial intelligence tasks. The requirements for platforms of this class and the principles for changing the design of the SoC for implementation in the prototype have been described as well as methods of debugging projects on the prototyping platform. The results of the work of computer vision algorithms using neural network technologies on the FPGA prototype of the ELcore semantic cores have been presented.

scholarly journals A proposal for a UPC memory consistency model, v1.0

2004 ◽  
Author(s):  
Katherine Yelick ◽  
Dan Bonachea ◽  
Charles Wallace
Keyword(s):  
Memory Consistency ◽  
Consistency Model ◽  
Memory Consistency Model

Optimized Communication Architecture of MPSoCs with a Hardware Scheduler

2011 ◽  
Vol 2 (3) ◽  
pp. 1-20 ◽  
Author(s):  
Diandian Zhang ◽  
Han Zhang ◽  
Jeronimo Castrillon ◽  
Torsten Kempf ◽  
Bart Vanthournout ◽  
...  
Keyword(s):  
High Performance ◽  
Programming Model ◽  
Real Life ◽  
Point Of View ◽  
Communication Architecture ◽  
Dynamic Task ◽  
Computational Performance ◽  
Systems On Chip ◽  
Promising Solution ◽  
On Chip

Efficient runtime resource management in multi-processor systems-on-chip (MPSoCs) for achieving high performance and low energy consumption is one of the key challenges for system designers. OSIP, an operating system application-specific instruction-set processor, together with its well-defined programming model, provides a promising solution. It delivers high computational performance to deal with dynamic task scheduling and mapping. Being programmable, it can easily be adapted to different systems. However, the distributed computation among the different processing elements introduces complexity to the communication architecture, which tends to become the bottleneck of such systems. In this work, the authors highlight the vital importance of the communication architecture for OSIP-based systems and optimize the communication architecture. Furthermore, the effects of OSIP and the communication architecture are investigated jointly from the system point of view, based on a broad case study for a real life application (H.264) and a synthetic benchmark application.

scholarly journals How Europe Is Preparing Its Core Solution for Exascale Machines and a Global, Sovereign, Advanced Computing Platform

2020 ◽  
Vol 25 (3) ◽  
pp. 46 ◽  
Author(s):  
Mario Kovač ◽  
Philippe Notton ◽  
Daniel Hofman ◽  
Josip Knezović
Keyword(s):  
High Performance ◽  
Embedded Software ◽  
Economic Viability ◽  
Computing Platform ◽  
Systems On Chip ◽  
The World ◽  
Core Solution ◽  
On Chip ◽  
Advanced Computing ◽  
Performance Computing

In this paper, we present an overview of the European Processor Initiative (EPI), one of the cornerstones of the EuroHPC Joint Undertaking, a new European Union strategic entity focused on pooling the Union’s and national resources on HPC to acquire, build and deploy the most powerful supercomputers in the world within Europe. EPI started its activities in December 2018. The first three years drew processor and platform designers, embedded software, middleware, applications and usage experts from 10 EU countries together to co-design Europe’s first HPC Systems on Chip and accelerators with its unique Common Platform (CP) technology. One of EPI’s core activities also takes place in the automotive sector, providing architectural solutions for a novel embedded high-performance computing (eHPC) platform and ensuring the overall economic viability of the initiative.

SOC DESIGN FOR WIRELESS COMMUNICATIONS

2011 ◽  
Vol 20 (08) ◽  
pp. 1505-1527 ◽  
Author(s):  
ZORAN STAMENKOVIĆ
Keyword(s):  
Error Detection ◽  
High Performance ◽  
Basic Knowledge ◽  
Embedded Devices ◽  
Chip Design ◽  
Wireless Applications ◽  
Systems On Chip ◽  
Early Error ◽  
Custom Hardware ◽  
On Chip

The paper emphasizes methods, architectures, and components for system-on-chip design. It describes the basic knowledge and skills for designing high-performance low-power embedded devices whose complexity increases exponentially, as so does the effort of designing them. Relying upon an appropriate design methodology which concentrates on reuse, executable specifications, and early error detection, these complexities can be mastered. The paper bundles these topics in order to provide a good understanding of all the problems involved. It shows how to go from description and verification to implementation and testing, presenting three systems-on-chip for three different wireless applications based on configurable processors and custom hardware accelerators.

scholarly journals Cosimulation of Power and Temperature Models at the SystemC/TLM for a Soft-Core Processor

2020 ◽  
Vol 2020 ◽  
pp. 1-7
Author(s):  
Zineb El Hariti ◽  
Abdelhakim Alali ◽  
Mohamed Sadik ◽  
Kaoutar Aamali
Keyword(s):  
High Performance ◽  
System Level ◽  
Limiting Factor ◽  
Power Budget ◽  
Technology Roadmap ◽  
Systems On Chip ◽  
Limited Power ◽  
Virtual Platform ◽  
On Chip ◽  
Technology Nodes

Nowadays, modern embedded applications are becoming more and more complex and resource demanding. Fortunately, Systems on Chip (SoC) are one of the keys used to follow their requirements that stand in need of high performance while maintaining a low-power profile. On one hand, today, due to the limited power budget imposed by the batteries, power is the limiting factor of the logic CMOS. On the other hand, the downscaling of the technology node for 65 nm and beyond, based on the International Technology Roadmap for Semiconductors (ITRS) as a reference, has not only resulted in huge energy consumption but also increased the temperature chip. To address this challenge, designing at the system level is the suitable measure to tackle with the complexity of the Systems on Chip, aiming at having better adjustment between timing and accuracy for power and temperature estimations. We present in this paper, at the first stage, two models describing the static and dynamic power at the physical level. These models are implemented on an open virtual platform Model Power-Consumption and Temperature in SystemC/TLM (LIBTLMPWT) based on a representative SoC architecture. At the second stage, we focus on power, especially the thermal behaviour of the chip while running three benchmarks set on the game of life application for two different technology nodes.

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