(Invited) Transparent Top Gate Oxide TFT with ITO/Ag/ITO Low Resistance Electrode for the Application to the High Speed Operation Fingerprint Sensor Array in the Touch Panel

Abstract Fundamental consideration for CDM (Charged Device Model) breakdown was investigated with 90nm technology products and others. According to the result of failure analysis, it was found that gate oxide breakdown was critical failure mode for CDM test. High speed triggered protection device such as ggNMOS and SCR (Thyristor) is effective method to improve its CDM breakdown voltage and an improvement for evaluated products were confirmed. Technological progress which is consisted of down-scaling of protection device size and huge number of IC pins of high function package makes technology vulnerable and causes significant CDM stress. Therefore, it is expected that CDM protection designing tends to become quite difficult. In order to solve these problems in the product, fundamental evaluations were performed. Those are a measurement of discharge parameter and stress time dependence of CDM breakdown voltage. Peak intensity and rise time of discharge current as critical parameters are well correlated their package capacitance. Increasing stress time causes breakdown voltage decreasing. This mechanism is similar to that of TDDB for gate oxide breakdown. Results from experiences and considerations for future CDM reliable designing are explained in this report.

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Multi-Touch Interaction Generation Device by Spatiotemporally Switching Electrodes

Electronics ◽

10.3390/electronics10121475 ◽

2021 ◽

Vol 10 (12) ◽

pp. 1475

Author(s):

Masahiro Okamoto ◽

Kazuya Murao

Keyword(s):

High Speed ◽

High Accuracy ◽

Conductive Ink ◽

Control Board ◽

Touch Panel ◽

Electrode Size ◽

Touch Input ◽

Touch Interaction ◽

Multiple Electrodes ◽

Touch Panels

With the spread of devices equipped with touch panels, such as smartphones, tablets, and laptops, the opportunity for users to perform touch interaction has increased. In this paper, we constructed a device that generates multi-touch interactions to realize high-speed, continuous, or hands-free touch input on a touch panel. The proposed device consists of an electrode sheet printed with multiple electrodes using conductive ink and a voltage control board, and generates eight multi-touch interactions: tap, double-tap, long-press, press-and-tap, swipe, pinch-in, pinch-out, and rotation, by changing the capacitance of the touch panel in time and space. In preliminary experiments, we investigated the appropriate electrode size and spacing for generating multi-touch interactions, and then implemented the device. From the evaluation experiments, it was confirmed that the proposed device can generate multi-touch interactions with high accuracy. As a result, tap, press-and-tap, swipe, pinch-in, pinch-out, and rotation can be generated with a success rate of 100%. It was confirmed that all the multi-touch interactions evaluated by the proposed device could be generated with high accuracy and acceptable speed.

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Development of high k/III-V (InGaAs, InAs, InSb) structures for future low power, high speed device applications

MRS Proceedings ◽

10.1557/opl.2013.585 ◽

2013 ◽

Vol 1538 ◽

pp. 291-302

Author(s):

Edward Yi Chang ◽

Hai-Dang Trinh ◽

Yueh-Chin Lin ◽

Hiroshi Iwai ◽

Yen-Ku Lin

Keyword(s):

Low Power ◽

Leakage Current ◽

High Speed ◽

High Performance ◽

Gate Oxide ◽

Chemical Cleaning ◽

Low Leakage ◽

Low Leakage Current ◽

High K ◽

Cleaning Methods

ABSTRACTIII-V compounds such as InGaAs, InAs, InSb have great potential for future low power high speed devices (such as MOSFETs, QWFETs, TFETs and NWFETs) application due to their high carrier mobility and drift velocity. The development of good quality high k gate oxide as well as high k/III-V interfaces is prerequisite to realize high performance working devices. Besides, the downscaling of the gate oxide into sub-nanometer while maintaining appropriate low gate leakage current is also needed. The lack of high quality III-V native oxides has obstructed the development of implementing III-V based devices on Si template. In this presentation, we will discuss our efforts to improve high k/III-V interfaces as well as high k oxide quality by using chemical cleaning methods including chemical solutions, precursors and high temperature gas treatments. The electrical properties of high k/InSb, InGaAs, InSb structures and their dependence on the thermal processes are also discussed. Finally, we will present the downscaling of the gate oxide into sub-nanometer scale while maintaining low leakage current and a good high k/III-V interface quality.

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