Fundamental Considerations for CDM Failure in 90nm Products

2006 ◽  
Author(s):  
Nobuyuki Wakai ◽  
Yuji Kobira ◽  
Hidemitsu Egawa ◽  
Masayoshi Tsutsumi
Keyword(s):  
Breakdown Voltage ◽  
High Speed ◽  
Gate Oxide ◽  
Critical Parameters ◽  
Protection Device ◽  
Oxide Breakdown ◽  
Technology Products ◽  
Charged Device ◽  
Device Size ◽  
Fundamental Consideration

Abstract Fundamental consideration for CDM (Charged Device Model) breakdown was investigated with 90nm technology products and others. According to the result of failure analysis, it was found that gate oxide breakdown was critical failure mode for CDM test. High speed triggered protection device such as ggNMOS and SCR (Thyristor) is effective method to improve its CDM breakdown voltage and an improvement for evaluated products were confirmed. Technological progress which is consisted of down-scaling of protection device size and huge number of IC pins of high function package makes technology vulnerable and causes significant CDM stress. Therefore, it is expected that CDM protection designing tends to become quite difficult. In order to solve these problems in the product, fundamental evaluations were performed. Those are a measurement of discharge parameter and stress time dependence of CDM breakdown voltage. Peak intensity and rise time of discharge current as critical parameters are well correlated their package capacitance. Increasing stress time causes breakdown voltage decreasing. This mechanism is similar to that of TDDB for gate oxide breakdown. Results from experiences and considerations for future CDM reliable designing are explained in this report.

A Study of Pad Contamination Defect and Removal

2008 ◽  
Author(s):  
K.A. Mohammad ◽  
L.J. Liu ◽  
S.F. Liew ◽  
S.F. Chong ◽  
D.G. Lee ◽  
...  
Keyword(s):  
Failure Analysis ◽  
Gate Oxide ◽  
Action Plans ◽  
Preventive Action ◽  
Oxide Breakdown ◽  
Reliability Level ◽  
The Future ◽  
Dry Etch ◽  
Removal Technique

Abstract The paper focuses on the pad contamination defect removal technique. The defect is detected at the outgoing inspection step. The failure analysis results showed that the defect is Fluorine type contamination. The failure analysis indicated many source contributors mainly from Fluorine based processes. The focus is in the present work is in the rework method for the removal of this defect. The combination of wet and dry etch processing in the rework routine is utilized for the removal of the defect and preventive action plans for in-line were introduced and implemented to avoid this event in the future. The reliability of the wafer is verified using various tests including full map electrical, electrical sort, gate oxide breakdown (GOI) and wafer reliability level, passivation quick kill to ensure the integrity of the wafer after undergoing the rework routine. The wafer is monitored closely over a period of time to ensure it has no mushroom defect.

Development of high k/III-V (InGaAs, InAs, InSb) structures for future low power, high speed device applications

2013 ◽  
Vol 1538 ◽  
pp. 291-302
Author(s):  
Edward Yi Chang ◽  
Hai-Dang Trinh ◽  
Yueh-Chin Lin ◽  
Hiroshi Iwai ◽  
Yen-Ku Lin
Keyword(s):  
Low Power ◽  
Leakage Current ◽  
High Speed ◽  
High Performance ◽  
Gate Oxide ◽  
Chemical Cleaning ◽  
Low Leakage ◽  
Low Leakage Current ◽  
High K ◽  
Cleaning Methods

ABSTRACTIII-V compounds such as InGaAs, InAs, InSb have great potential for future low power high speed devices (such as MOSFETs, QWFETs, TFETs and NWFETs) application due to their high carrier mobility and drift velocity. The development of good quality high k gate oxide as well as high k/III-V interfaces is prerequisite to realize high performance working devices. Besides, the downscaling of the gate oxide into sub-nanometer while maintaining appropriate low gate leakage current is also needed. The lack of high quality III-V native oxides has obstructed the development of implementing III-V based devices on Si template. In this presentation, we will discuss our efforts to improve high k/III-V interfaces as well as high k oxide quality by using chemical cleaning methods including chemical solutions, precursors and high temperature gas treatments. The electrical properties of high k/InSb, InGaAs, InSb structures and their dependence on the thermal processes are also discussed. Finally, we will present the downscaling of the gate oxide into sub-nanometer scale while maintaining low leakage current and a good high k/III-V interface quality.

Explanation of nMOSFET substrate current after hard gate oxide breakdown

2001 ◽  
Vol 59 (1-4) ◽  
pp. 155-160 ◽  
Author(s):  
B Kaczer ◽  
R Degraeve ◽  
A De Keersgieter ◽  
M Rasras ◽  
G Groeseneken
Keyword(s):  
Gate Oxide ◽  
Oxide Breakdown ◽  
Substrate Current

Dependence of Reliability of Ultrathin Mos Gate Oxides on the Fermi Level Positions at Gate and Substrate

1997 ◽  
Vol 473 ◽  
Author(s):  
Tien-Chun Yang ◽  
Navakanta Bhat ◽  
Krishna C. Saraswat
Keyword(s):  
Electric Field ◽  
Fermi Level ◽  
Breakdown Strength ◽  
Gate Oxide ◽  
High Energy ◽  
Constant Current ◽  
Oxide Breakdown ◽  
Mos Devices ◽  
High Energy Electrons ◽  
Substrate Doping

ABSTRACTWe demonstrate that the reliability of ultrathin (< 10 nm) gate oxide in MOS devices depends on the Fermi level position at the gate, and not on the position at the substrate for constant current gate injection (Vg-). The oxide breakdown strength (Qbd) is less for p+ poly-Si gate than for n+ poly-Si gate, but, it is independent of the substrate doping type. The degradation of oxides is closely related to the electric field across the gate oxide, which is influenced by the cathode Fermi level. P+ poly-Si gate has higher barrier height for tunneled electrons, therefore, the cathode electric field must be higher to give the same injection current density. A higher electric field gives more high energy electrons at the anode, and therefore the damage is more at the substrate interface. Different substrate types cause no effect on the oxide electric field, and as a result, they do not influence the degradation.

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