Impact on the Conductance Method of the Asymmetry in the AC Response Induced by Interface Trap Levels

2021 ◽  
Author(s):  
Hsin-Jyun Lin ◽  
Hiroshi Watanabe ◽  
Akinobu Teramoto ◽  
Rihito Kuroda ◽  
Kota Umezawa ◽  
...  
Keyword(s):  
Interface Trap ◽  
Conductance Method ◽  
The Asymmetry ◽  
Ac Response ◽  
Trap Levels

Monitoring on Creation and Annihilation of Interface Trap Levels with NO Oxidation, Re-Oxidation and N2 Annealing with Conductance Measurements

2020 ◽  
Vol 1004 ◽  
pp. 595-600
Author(s):  
Xiang Zhou ◽  
Collin W. Hitchcock ◽  
Rajendra P. Dahal ◽  
Gyanesh Pandey ◽  
Jacob Kupernik ◽  
...  
Keyword(s):  
Gate Oxide ◽  
Metal Oxide Semiconductor ◽  
No Oxidation ◽  
Oxide Semiconductor ◽  
Electron Trapping ◽  
Process Conditions ◽  
Interface Trap ◽  
Annihilation Process ◽  
Mos Capacitors ◽  
Trap Levels

We have determined, using the Conductance-Frequency (G-ω) Technique, the creation and annihilation process of the 3 interface trap levels (OX, OX’ and NI levels) previously reported [1-3] and their possible correlation to inversion electron trapping and mobilities. The measurements were carried out on various 4H-SiC Metal Oxide Semiconductor (MOS) capacitors that have been processed using several gate oxide processes [2,5,6]. Our analysis focus on the correlation of the interface trap levels on the process conditions so as to first understand and then control their formation.

scholarly journals Steep Subthreshold Swing and Enhanced Illumination Stability InGaZnO Thin-Film Transistor by Plasma Oxidation on Silicon Nitride Gate Dielectric

Membranes ◽  
2021 ◽  
Vol 11 (11) ◽  
pp. 902
Author(s):  
Yiming Liu ◽  
Chang Liu ◽  
Houyun Qin ◽  
Chong Peng ◽  
Mingxin Lu ◽  
...  
Keyword(s):  
Thin Film ◽  
Silicon Nitride ◽  
Oxygen Vacancy ◽  
High Performance ◽  
Gate Dielectric ◽  
Thin Film Transistor ◽  
Subthreshold Swing ◽  
Interface Trap ◽  
Plasma Oxidation ◽  
Conductance Method

In this paper, an InGaZnO thin-film transistor (TFT) based on plasma oxidation of silicon nitride (SiNx) gate dielectric with small subthreshold swing (SS) and enhanced stability under negative bias illumination stress (NBIS) have been investigated in detail. The mechanism of the high-performance InGaZnO TFT with plasma-oxidized SiNx gate dielectric was also explored. The X-ray photoelectron spectroscopy (XPS) results confirmed that an oxygen-rich layer formed on the surface of the SiNx layer and the amount of oxygen vacancy near the interface between SiNx and InGaZnO layer was suppressed via pre-implanted oxygen on SiNx gate dielectric before deposition of the InGaZnO channel layer. Moreover, the conductance method was employed to directly extract the density of the interface trap (Dit) in InGaZnO TFT to verify the reduction in oxygen vacancy after plasma oxidation. The proposed InGaZnO TFT with plasma oxidation exhibited a field-effect mobility of 16.46 cm2/V·s, threshold voltage (Vth) of −0.10 V, Ion/Ioff over 108, SS of 97 mV/decade, and Vth shift of −0.37 V after NBIS. The plasma oxidation on SiNx gate dielectric provides a novel approach for suppressing the interface trap for high-performance InGaZnO TFT.

Analysis of Interface Trap Densities for Al2O3 Dielectric Material Based Ultra Thin MOS Devices

2016 ◽  
Vol 860 ◽  
pp. 25-29 ◽  
Author(s):  
Niladri Pratap Maity ◽  
Rajiv R. Thakur ◽  
Reshmi Maity ◽  
R.K. Thapa ◽  
S. Baishya
Keyword(s):  
Dielectric Material ◽  
Oxide Thickness ◽  
Oxide Semiconductor ◽  
Interface Trap ◽  
Mos Devices ◽  
Novel Approach ◽  
High K ◽  
Conductance Method ◽  
High K Dielectric ◽  
P Type

In this paper the interface trap densities (Dit) are analyzed for ultra thin dielectric material based metal oxide semiconductor (MOS) devices using high-k dielectric material Al2O3. The Dit have been calculated by a novel approach using conductance method and it indicates that by reducing the thickness of the oxide, the Dit increases and similar increase is also found by replacing SiO2 with Al2O3. For the same oxide thickness SiO2 has the lowest Dit and found to be the order of 1011 cm-2eV-1. The Dit is found to be in good agreement with published fabrication results at p-type doping level of 1 × 1017 cm-3. Numerical calculations and solutions are performed by MATLAB and device simulation is done by ATLAS.

Electrical Characterization of GaN Metal Oxide Semiconductor Diodes Using MgO as the Gate Oxide

2001 ◽  
Vol 693 ◽  
Author(s):  
J. Kim ◽  
B. P. Gila ◽  
R. Mehandru ◽  
J.W. Johnson ◽  
J. H. Shin ◽  
...  
Keyword(s):  
Metal Oxide ◽  
Electron Cyclotron Resonance ◽  
Gate Oxide ◽  
State Density ◽  
Metal Oxide Semiconductor ◽  
Trap Density ◽  
Oxide Semiconductor ◽  
Interface Trap Density ◽  
Interface Trap ◽  
Conductance Method

AbstractGaN metal oxide semiconductor diodes were demonstrated utilizing MgO as the gate oxide. MgO was grown at 100°C on MOCVD grown n-GaN in a molecular beam epitaxy system using a Mg elemental source and an electron cyclotron resonance oxygen plasma. H3PO4 based wet-chemical etchant was used to remove MgO to expose the underlying n-GaN for ohmic metal deposition. Electron deposited Ti/Al/Pt/Au and Pt/Au were utilized as ohmic and gate metallization, respectively. An interface trap density of low-to-mid 1011 eV-1cm-2was obtained from temperature conductance-voltage measurements. Terman method was also used to estimate the interface trap density and a slight lower number was obtained as compared to the conductance method. Results from elevated temperature (up to 300°C) conductance measurements showed an interface state density roughly three times higher(6x1011 eV–1 cm-2 ) than at 25°C.

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