Analysis of Interface Trap Densities for Al2O3 Dielectric Material Based Ultra Thin MOS Devices

2016 ◽  
Vol 860 ◽  
pp. 25-29 ◽  
Author(s):  
Niladri Pratap Maity ◽  
Rajiv R. Thakur ◽  
Reshmi Maity ◽  
R.K. Thapa ◽  
S. Baishya
Keyword(s):  
Dielectric Material ◽  
Oxide Thickness ◽  
Oxide Semiconductor ◽  
Interface Trap ◽  
Mos Devices ◽  
Novel Approach ◽  
High K ◽  
Conductance Method ◽  
High K Dielectric ◽  
P Type

In this paper the interface trap densities (Dit) are analyzed for ultra thin dielectric material based metal oxide semiconductor (MOS) devices using high-k dielectric material Al2O3. The Dit have been calculated by a novel approach using conductance method and it indicates that by reducing the thickness of the oxide, the Dit increases and similar increase is also found by replacing SiO2 with Al2O3. For the same oxide thickness SiO2 has the lowest Dit and found to be the order of 1011 cm-2eV-1. The Dit is found to be in good agreement with published fabrication results at p-type doping level of 1 × 1017 cm-3. Numerical calculations and solutions are performed by MATLAB and device simulation is done by ATLAS.

Analysis of Interface Charge Densities for High-k Dielectric Materials based Metal Oxide Semiconductor Devices

2016 ◽  
Vol 15 (05n06) ◽  
pp. 1660011 ◽  
Author(s):  
N. P. Maity ◽  
R. R. Thakur ◽  
Reshmi Maity ◽  
R. K. Thapa ◽  
S. Baishya
Keyword(s):  
Metal Oxide ◽  
Oxide Thickness ◽  
Dielectric Materials ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Charge Densities ◽  
Interface Charge ◽  
High K ◽  
Conductance Method ◽  
High K Dielectric

In this paper, the interface charge densities ([Formula: see text]) are studied and analyzed for ultra thin dielectric metal oxide semiconductor (MOS) devices using different high-k dielectric materials such as Al2O3, ZrO2 and HfO2. The [Formula: see text] have been calculated by a new approach using conductance method and it indicates that by reducing the thickness of the oxide, the [Formula: see text] increases and similar increase is also found by replacing SiO2 with high-k. For the same oxide thickness, SiO2 has the lowest [Formula: see text] and found to be the order of 10[Formula: see text][Formula: see text]cm[Formula: see text][Formula: see text]eV[Formula: see text]. Linear increase in [Formula: see text] has been observed as the dielectric constant of the oxide increases. The [Formula: see text] is found to be in good agreement with published fabrication results at p-type doping level of [Formula: see text][Formula: see text]cm[Formula: see text]. Numerical calculations and solutions are performed by MATLAB and device simulation is done by ATLAS.

A tunneling current density model for ultra thin HfO2 high-k dielectric material based MOS devices

2016 ◽  
Vol 95 ◽  
pp. 24-32 ◽  
Author(s):  
Niladri Pratap Maity ◽  
Reshmi Maity ◽  
R.K. Thapa ◽  
Srimanta Baishya
Keyword(s):  
Current Density ◽  
Dielectric Material ◽  
Tunneling Current ◽  
Density Model ◽  
Mos Devices ◽  
High K ◽  
High K Dielectric

scholarly journals Numerical simulation of Gate shape effect on Self-Heating in nano-MOSFET Transistors with high-k dielectric

2021 ◽  
Author(s):  
Maissa Belkheria ◽  
Fraj Echouchene ◽  
Abdullah Bajahzar ◽  
hafedh belmabrouk
Keyword(s):  
Dielectric Material ◽  
Oxide Thickness ◽  
Shape Effect ◽  
Heating Effect ◽  
The Finite Element Method ◽  
Self Heating ◽  
High K ◽  
High K Dielectric ◽  
Semiconductor Equations ◽  
Nano Mosfet

Abstract The aim of the present work is to investigate numerically the self-heating effect (SHE) in MOSFET transistors based on high-k material taking into account the deformation of the gate under the SHE. The SHE inside the MOSFET transistor is calculated using the electrothermal model based on heat transfer equation coupled with semiconductor equations. The electrothermal model have been solved in 2D-dimension using the finite element method. The high-k dielectric HfO2 have been used as gate oxide. Several gate shapes have been used to analyze their impact on SHE. It is observed that the reduction of equivalent oxide thickness (EOT) reduces the SHE in the MOSFET transistor based in high-k dielectric material. the temperature peak increases quadratically with drain voltage for all MOSFET structures. A decrease in self-heating effect is achieved using the square gate shape.

Improved Switching Characteristics Obtained by Using High-k Dielectric Layers in 4H-SiC IGBT: Physics-Based Simulation

2017 ◽  
Vol 897 ◽  
pp. 571-574 ◽  
Author(s):  
Vidya Naidu ◽  
Sivaprasad Kotamraju
Keyword(s):  
Switching Frequency ◽  
Power Losses ◽  
Switching Power ◽  
Mos Devices ◽  
High K ◽  
High Switching Frequency ◽  
Switching Characteristics ◽  
High K Dielectric ◽  
Current Duration ◽  
Physics Based Simulation

Silicon Carbide (SiC) based MOS devices are one of the promising devices for high temperature, high switching frequency and high power applications. In this paper, the static and dynamic characteristics of an asymmetric trench gate SiC IGBT with high-k dielectrics- HfO2 and ZrO2 are investigated. SiC IGBT with HfO2 and ZrO2 exhibited higher forward transconductance ratio and lower threshold voltage compared to conventionally used SiO2. In addition, lower switching power losses have been observed in the case of high-k dielectrics due to reduced tail current duration.

scholarly journals Conformal High-K Dielectric Coating of Suspended Single-Walled Carbon Nanotubes by Atomic Layer Deposition

Nanomaterials ◽  
2019 ◽  
Vol 9 (8) ◽  
pp. 1085 ◽  
Author(s):  
Kemelbay ◽  
Tikhonov ◽  
Aloni ◽  
Kuykendall
Keyword(s):  
Carbon Nanotubes ◽  
Atomic Layer Deposition ◽  
Field Effect Transistors ◽  
Atomic Layer ◽  
Oxide Thickness ◽  
Ambient Conditions ◽  
Nucleation Layer ◽  
Layer Deposition ◽  
High K ◽  
High K Dielectric

As one of the highest mobility semiconductor materials, carbon nanotubes (CNTs) have been extensively studied for use in field effect transistors (FETs). To fabricate surround-gate FETs— which offer the best switching performance—deposition of conformal, weakly-interacting dielectric layers is necessary. This is challenging due to the chemically inert surface of CNTs and a lack of nucleation sites—especially for defect-free CNTs. As a result, a technique that enables integration of uniform high-k dielectrics, while preserving the CNT’s exceptional properties is required. In this work, we show a method that enables conformal atomic layer deposition (ALD) of high-k dielectrics on defect-free CNTs. By depositing a thin Ti metal film, followed by oxidation to TiO2 under ambient conditions, a nucleation layer is formed for subsequent ALD deposition of Al2O3. The technique is easy to implement and is VLSI-compatible. We show that the ALD coatings are uniform, continuous and conformal, and Raman spectroscopy reveals that the technique does not induce defects in the CNT. The resulting bilayer TiO2/Al2O3 thin-film shows an improved dielectric constant of 21.7 and an equivalent oxide thickness of 2.7 nm. The electrical properties of back-gated and top-gated devices fabricated using this method are presented.

scholarly journals Current Tunnelling in MOS Devices with Al2O3/SiO2 Gate Dielectric

2008 ◽  
Vol 2008 ◽  
pp. 1-5 ◽  
Author(s):  
A. Bouazra ◽  
S. Abdi-Ben Nasrallah ◽  
M. Said ◽  
A. Poncet
Keyword(s):  
Dielectric Constant ◽  
Gate Dielectric ◽  
Oxide Thickness ◽  
Gate Leakage ◽  
Mos Devices ◽  
High K ◽  
Carrier Trap ◽  
High Dielectric ◽  
Very High ◽  
Tunnelling Current

With the continued scaling of the SiO2 thickness below 2 nm in CMOS devices, a large direct-tunnelling current flow between the gate electrode and silicon substrate is greatly impacting device performance. Therefore, higher dielectric constant materials are desirable for reducing the gate leakage while maintaining transistor performance for very thin dielectric layers. Despite its not very high dielectric constant (∼10), Al2O3 has emerged as one of the most promising high-k candidates in terms of its chemical and thermal stability as its high-barrier offset. In this paper, a theoretical study of the physical and electrical properties of Al2O3 gate dielectric is reported including I(V) and C(V) characteristics. By using a stack of Al2O3/SiO2 with an appropriate equivalent oxide thickness of gate dielectric MOS, the gate leakage exhibits an important decrease. The effect of carrier trap parameters (depth and width) at the Al2O3/SiO2 interface is also discussed.

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