Pore Sealing for Low-k Delectric Integration into Integrated Circuits

2005 ◽  
Keyword(s):  
Integrated Circuits ◽  
Pore Sealing ◽  
Low K

Pore sealing of SiOCH ultra low-k dielectrics with polyimide Langmuir-Blodgett film

2012 ◽  
Vol 1428 ◽  
Author(s):  
S.I. Goloudina ◽  
A. S. Ivanov ◽  
M. B. Krishtab ◽  
V.V. Luchinin ◽  
V.M. Pasyuta ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
Deposition Process ◽  
Dielectric Materials ◽  
K Value ◽  
Langmuir Blodgett ◽  
Air Interface ◽  
Pore Sealing ◽  
Materials Used ◽  
High Dielectric ◽  
Low K

ABSTRACTContinuous decrease of the feature size of transistors in modern integrated circuits (ICs) constrains thickness of auxiliary dielectric layers in interconnects because of their relatively high dielectric constant, which reduces the efficiency of low-k material integration. Dielectric materials used today as barrier or etch-stop layers are usually SiN (k ∼ 7.0) and SiCN (k ∼ 4.8), which k-value significantly exceeds that of recent ultra low-k materials (k < 2.2). In our work we have investigated thin films of rigid-chain polyimide (PI) with a k-value of about 3.2-3.3. This film was deposited using a Langmuir-Blodgett (LB) technique and can be as thin as several monolayers. The intermolecular interaction of densely packed precursor macromolecules within a monolayer formed at the water-air interface makes it possible to avoid penetration of precursor material inside the pores. The latter peculiarity of the deposition process results in a pore sealing effect using a 4 nm PI film.

Study of Porous Silica Based Films as Low-k Dielectric Material and their Interface with Copper Metallization

2002 ◽  
Vol 716 ◽  
Author(s):  
Ilanit Fisher ◽  
Wayne D. Kaplan ◽  
Moshe Eizenberg ◽  
Michael Nault ◽  
Timothy Weidman
Keyword(s):  
Integrated Circuits ◽  
Dielectric Material ◽  
Hydrogen Plasma ◽  
Porous Silica ◽  
Film Deposition ◽  
Copper Metallization ◽  
High Porosity ◽  
Tem Analysis ◽  
Chip Technology ◽  
Low K

AbstractThe success of future gigascale integrated circuits (IC) chip technology depends critically upon the reduction of the interconnects RC delay time. This calls for the development of new low dielectric constant (low-k) insulators, and for work on their integration with lower resistivity copper metallization.A porous silica based film prepared by surfactant templated self-assembly spin-on deposition (SOD) is an attractive candidate as a low-k material. In this research we have studied the structure, chemical composition and bonding of the film and its interface with copper metallization. The decomposition and vaporization of the surfactant in the last step of film deposition resulted in a film with an amorphous structure, as determined by XRD and TEM analysis. Its high porosity (35-58%) was confirmed by XRR and RBS measurements. XPS analysis of the Si2p transition indicated three types of bonding: Si-O, O-Si-C and Si-C. The bonding characteristics were also investigated by FTIR analysis. The effect of a hydrogen plasma post-treatment process on the film topography and bonding was determined by AFM and XPS, respectively. It was found that direct H2 plasma exposure significantly affected the surface roughness of the film and type of chemical bonding. The structure and properties of various PECVD deposited capping layers were also studied, as was the interface between the porous dielectric and Ta, TaxN and Cu (PVD deposited films) after annealing at 200-700°C in vacuum environment for 30 min. At temperatures up to 500°C, no significant diffusion of Cu or Ta into the porous film was detected, as determined by RBS. No copper penetration was detected up to 700°C, according to AES and SIMS analysis. However, at 700°C copper dewetting occurred when it was deposited directly on the porous silica based film.

C4 EM and CPI Reliability Benefits and Process Challenges of FBEOL Integration Changes Implemented in Lead-free C4 Products

2015 ◽  
Vol 2015 (1) ◽  
pp. 000787-000792
Author(s):  
E. Misra ◽  
T. Wassick ◽  
I. Melville ◽  
K. Tunga ◽  
D. Questad ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
Flip Chip ◽  
Process Integration ◽  
Semiconductor Industry ◽  
Lead Free ◽  
Solder Interconnects ◽  
Design Changes ◽  
Modeling Data ◽  
Free Solder ◽  
Low K

The introduction of low-k & ultra-low-k dielectrics, lead-free (Pb-free) solder interconnects or C4's, and organic flip-chip laminates for integrated circuits have led to some major reliability challenges for the semiconductor industry. These include C4 electromigration (EM) and mechanical failures induced with-in the Si chip due to chip-package interactions (CPI). In 32nm technology, certain novel design changes were evaluated in the last Cu wiring level and the Far Back End of Line levels (FBEOL) to strategically re-distribute the current more uniformly through the Pb-free C4 bumps and therefore improve the C4 EM capabilities of the technology. FBEOL process integration changes, such as increasing the thickness of the hard dielectric (SiNx & SiOx) and reducing the final via diameter, were also evaluated for reducing the mechanical stresses in the weaker BEOL levels and mitigating potential risks for mechanical failures within the Si chip. The supporting white-bump, C4 EM and electrical/mechanical modeling data that demonstrates the benefits of the design and integration changes will be discussed in detail in the paper. Some of the key processing and integration challenges observed due to the design and process updates and the corresponding mitigation steps taken will also be discussed.

Restoration and pore sealing of low-k films by UV-assisted processes

2014 ◽  
Author(s):  
Bo Xie ◽  
Kelvin Chan ◽  
David Cui ◽  
He Ren ◽  
Daemian Raj ◽  
...  
Keyword(s):  
Pore Sealing ◽  
Low K

Reliability analysis method for low-k interconnect dielectrics breakdown in integrated circuits

2005 ◽  
Vol 98 (3) ◽  
pp. 034503 ◽  
Author(s):  
Gaddi S. Haase ◽  
Ennis T. Ogawa ◽  
Joe W. McPherson
Keyword(s):  
Integrated Circuits ◽  
Reliability Analysis ◽  
Analysis Method ◽  
Low K

Ultra- Thin Conformal Pore-Sealing of Low-k Materials by Plasma-Assisted ALD

2019 ◽  
Vol 11 (7) ◽  
pp. 167-176
Author(s):  
Joseph L. Cecchi ◽  
C. Jeffrey Brinker ◽  
Ying-Bing Jiang
Keyword(s):  
Pore Sealing ◽  
Low K

The Effect of Ar/H2 Plasma Pretreatments on Porous K=2.0 Dielectrics for Pore Sealing by Self-Assembled Monolayers Deposition

2012 ◽  
Vol 195 ◽  
pp. 146-149 ◽  
Author(s):  
Y. Sun ◽  
J. Swerts ◽  
P. Verdonck ◽  
A. Maheshwari ◽  
J.L. Prado ◽  
...  
Keyword(s):  
Plasma Temperature ◽  
Self Assembled Monolayers ◽  
Hydroxyl Groups ◽  
K Value ◽  
Oh Groups ◽  
Surface Hydroxyl ◽  
Pore Sealing ◽  
Assembled Monolayers ◽  
Self Assembled ◽  
Low K

Self-assembled monolayers (SAMs) deposition is being recently explored to help sealing the pores of a k=2.0 material. In order to enable a covalent chemical low-k surface functionalization by SAMs, a hydroxyl groups density as high as 1 to 2.5 OH groups/nm2 is required. This surface modification must be carefully controlled to confine the k below 10%. In this paper, the effects of plasma temperature, time and power on the SAMs deposition and plasma-induced damage are investigated. The main findings are that there is always a trade-off between surface hydroxyl groups density and bulk damage. A thick modified layer allows the SAM molecules to penetrate inside the pores which results in a decreased porosity and an increased k value with respect to correspondent plasma-treated pristine substrates.

Sealing of low-k dielectric (k=2.0) with self-assembled monolayers (SAMs) for the atomic layer deposition (ALD) of TiN

2013 ◽  
Vol 1559 ◽  
Author(s):  
Yiting Sun ◽  
Elisabeth Levrau ◽  
Michiel Blauw ◽  
Johan Meersschaut ◽  
Patrick Verdonck ◽  
...  
Keyword(s):  
Atomic Layer ◽  
Self Assembled Monolayers ◽  
Low Dielectric Constant ◽  
Hydroxyl Groups ◽  
Low Dielectric ◽  
Tin Film ◽  
Layer Deposition ◽  
Pore Sealing ◽  
Assembled Monolayers ◽  
Low K

ABSTRACTIn this work, a novel low dielectric constant (low-k) pore sealing approach was engineered by depositing firstly a sub-2 nm SAMs and then a 3 nm TiN barrier film. The low-k film was pretreated by plasma to introduce hydroxyl groups onto the surface, followed by SAMs deposition. Then a TiN film was deposited from tetrakis(dimethylamino)titanium (TDMAT) via ALD as a dielectric barrier. Penetration of Ti atoms into low-k was measured and used to evaluate the sealing ability of SAMs. For the samples covered with SAMs, around 90% reduction of Ti atoms penetration was achieved. The pore radius was reduced to below 0.5 nm after the barrier deposition. The ∆k after pretreatment and after SAMs are 0.1 and 0.16, respectively.

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