Study of Porous Silica Based Films as Low-k Dielectric Material and their Interface with Copper Metallization

2002 ◽  
Vol 716 ◽  
Author(s):  
Ilanit Fisher ◽  
Wayne D. Kaplan ◽  
Moshe Eizenberg ◽  
Michael Nault ◽  
Timothy Weidman
Keyword(s):  
Integrated Circuits ◽  
Dielectric Material ◽  
Hydrogen Plasma ◽  
Porous Silica ◽  
Film Deposition ◽  
Copper Metallization ◽  
High Porosity ◽  
Tem Analysis ◽  
Chip Technology ◽  
Low K

AbstractThe success of future gigascale integrated circuits (IC) chip technology depends critically upon the reduction of the interconnects RC delay time. This calls for the development of new low dielectric constant (low-k) insulators, and for work on their integration with lower resistivity copper metallization.A porous silica based film prepared by surfactant templated self-assembly spin-on deposition (SOD) is an attractive candidate as a low-k material. In this research we have studied the structure, chemical composition and bonding of the film and its interface with copper metallization. The decomposition and vaporization of the surfactant in the last step of film deposition resulted in a film with an amorphous structure, as determined by XRD and TEM analysis. Its high porosity (35-58%) was confirmed by XRR and RBS measurements. XPS analysis of the Si2p transition indicated three types of bonding: Si-O, O-Si-C and Si-C. The bonding characteristics were also investigated by FTIR analysis. The effect of a hydrogen plasma post-treatment process on the film topography and bonding was determined by AFM and XPS, respectively. It was found that direct H2 plasma exposure significantly affected the surface roughness of the film and type of chemical bonding. The structure and properties of various PECVD deposited capping layers were also studied, as was the interface between the porous dielectric and Ta, TaxN and Cu (PVD deposited films) after annealing at 200-700°C in vacuum environment for 30 min. At temperatures up to 500°C, no significant diffusion of Cu or Ta into the porous film was detected, as determined by RBS. No copper penetration was detected up to 700°C, according to AES and SIMS analysis. However, at 700°C copper dewetting occurred when it was deposited directly on the porous silica based film.

The Study of Fluorinated Amorphous Carbon as Low-K Dielectric Material and its Interface with Copper Metallization

1999 ◽  
Vol 565 ◽  
Author(s):  
N. Ariel ◽  
M. Eizenberg ◽  
E. Y. Tzou
Keyword(s):  
Amorphous Carbon ◽  
Nuclear Reactions ◽  
Dielectric Material ◽  
Copper Metallization ◽  
Limiting Factor ◽  
Adhesion Promoter ◽  
Adhesion Promotion ◽  
High Resolution Tem ◽  
Rc Delay ◽  
Low K

AbstractIn order to achieve better performance of devices, the interconnects RC delay time, the limiting factor of the device speed today, must be reduced. This calls for a new interconnect stack: lower resistivity Copper and low k materials (k<3) as dielectrics.Fluorinated amorphous carbon (a-F:C) prepared by HDP- CVD is an attractive candidate as a low-k material. In this work we have studied the film, its stability and its interface with Copper metallization. The high density plasma CVD process resulted in a film which contains C and F at a ratio of 1:0.6 as determined by Nuclear Reactions Analysis. XPS analysis of the Cls transition indicated four types of bonds: C-C, C-CF, CF, and CF2. X-ray diffraction as well as high resolution TEM analyses proved that the film was amorphous at least up to 500°C anneal. For various applications, the advantage of adding a thin bi-layer of a-SiC/SiOx for adhesion promotion purposes was demonstrated. In addition, the interface of a-F:C and the adhesion promoter layer with Ta, TaN and Cu was studied. No interdiffusion was observed by SIMS after 400°C annealing. 500°C annealing caused F outdiffusion from the film and Cu diffusion into the adhesion promoter layer.

The Study of Fluorinated Amorphous Carbon as Low-K Dielectric Material and its Interface with Copper Metallization

1999 ◽  
Vol 564 ◽  
Author(s):  
N. Ariel ◽  
M. Eizenberg ◽  
E. Y. Tzou
Keyword(s):  
Amorphous Carbon ◽  
Nuclear Reactions ◽  
Dielectric Material ◽  
Copper Metallization ◽  
Limiting Factor ◽  
Adhesion Promoter ◽  
Adhesion Promotion ◽  
High Resolution Tem ◽  
Rc Delay ◽  
Low K

AbstractIn order to achieve better performance of devices, the interconnects RC delay time, the limiting factor of the device speed today, must be reduced. This calls for a new interconnect stack: lower resistivity Copper and low k materials (k<3) as dielectrics.Fluorinated amorphous carbon (a-F:C) prepared by HDP- CVD is an attractive candidate as a low-k material. In this work we have studied the film, its stability and its interface with Copper metallization. The high density plasma CVD process resulted in a film which contains C and F at a ratio of 1:0.6 as determined by Nuclear Reactions Analysis. XPS analysis of the C Is transition indicated four types of bonds: C-C, C-CF, CF, and CF2. X-ray diffraction as well as high resolution TEM analyses proved that the film was amorphous at least up to 500°C anneal. For various applications, the advantage of adding a thin bi-layer of a-SiC/SiOx for adhesion promotion purposes was demonstrated. In addition, the interface of a-F:C and the adhesion promoter layer with Ta, TaN and Cu was studied. No interdiffusion was observed by SIMS after 400°C annealing. 500°C annealing caused F outdiffusion from the film and Cu diffusion into the adhesion promoter layer.

Surfactants in Controlling Removal Rates and Selectivity in Barrier Slurry for Cu CMP

2007 ◽  
Vol 991 ◽  
Author(s):  
Jinru Bian
Keyword(s):  
Integrated Circuits ◽  
Dielectric Material ◽  
Removal Rate ◽  
Leading Edge ◽  
Dielectric Surface ◽  
Wafer Surface ◽  
Capping Layer ◽  
Charge Interaction ◽  
High Removal Rate ◽  
Low K

ABSTRACTLeading edge integrated circuits (ICs) are complicated structures designed to have up to 3 capping layers above a low k dielectric material. The upper capping layer may use TEOS and/or silicon nitride (SiN), while the lower one may use silicon carbon nitride (SiCN), silicon carbide (SiC), or carbon doped oxide (CDO) immediately above the low k dielectric. Therefore, a barrier slurry for copper CMP, in addition to exhibiting a high removal rate of the barrier, must be able to remove the upper capping layer and stop at the underlying dielectric surface.We have developed a slurry family that can effectively remove TaN, TEOS, SiN, CDO, and/or SiCN, or any combination of these films, or can stop at any one or two film surfaces of TEOS, SiN, CDO, SiCN, and SiC, depending on the specific slurry design. Removal rate control is achieved by one or two additives. One of the additives is an anionic surfactant. When selecting a surfactant, the surfactant hydrophobicity and charge interaction between the surfactant and the wafer surface are two important factors to be considered. This report discusses these two factors in selecting a proper surfactant for a specific slurry application.

Porous Silica Xerogel Processing And Integration For Ulsi Applications

1998 ◽  
Vol 511 ◽  
Author(s):  
Changming Jin ◽  
Scott List ◽  
Eden Zielinski
Keyword(s):  
Dielectric Constant ◽  
Dielectric Material ◽  
Porous Silica ◽  
Thin Film Deposition ◽  
Deposition Process ◽  
Film Deposition ◽  
Silica Xerogel ◽  
Future Technology ◽  
Small Pore ◽  
High Dielectric

ABSTRACTWith a tunable ultra low dielectric constant, porous silica xerogel is an attractive dielectric material for ULSI interconnect applications and is potentially extendable to multiple future technology nodes. Porous silica xerogel films have been processed and integrated into device test structures as ultra low k intermetal dielectrics. A fully automated thin film deposition process is recently developed and gives high throughput and good repeatability. A surface modification technique is used to make the films hydrophobic. The film dielectric constant is measured to be less than 2, depending on porosity. Because of the small pore sizes, the films display high dielectric break down strength. With proper shrinkage control, porous silica xerogel shows excellent gapfill capabilities. Integration of the porous silica xerogel material into CMP planarized double level metal (DLM) test structures with both Al and W plugs in a gapfill scheme is successful. Porous silica xerogel structures provide 14% and 35% total capacitance reduction compared to structures with hydrogen silsesquioxane (HSQ) and high density plasma (HDP) oxide respectively. Reliability and current leakage data of porous silica xerogel are comparable to that of HSQ. Feasibility of integrating porous silica xerogel into Cu damascene structures is also demonstrated. Cu/xerogel damascene structures exhibit improvements in both resistance and capacitance compared with convention Al/Oxide gapfill structures.

Reliability of Wire Bonding on Low-k Dielectric Material in Damascene Copper Integrated Circuits PBGA Assembly

2002 ◽  
Vol 42 (9-11) ◽  
pp. 1535-1540 ◽  
Author(s):  
Mohandass Sivakumar ◽  
Vaidyanathan Kripesh ◽  
Chong Ser Choong ◽  
Chai Tai Chong ◽  
Loon Aik Lim
Keyword(s):  
Integrated Circuits ◽  
Dielectric Material ◽  
Wire Bonding ◽  
Low K

Effects of BEOL Stack on Thermal Mechanical Stress of Cu Lines

2006 ◽  
Vol 914 ◽  
Author(s):  
Seung-Hyun Rhee ◽  
Conal E. Murray ◽  
Paul R. Besser
Keyword(s):  
Thermal Stress ◽  
Integrated Circuits ◽  
Structural Integrity ◽  
Dielectric Material ◽  
Dielectric Materials ◽  
X Ray Diffraction ◽  
And Control ◽  
Measurement And Control ◽  
Low K

AbstractThe measurement and control of the stress state in BEOL interconnects are important to ensure structural integrity and long term reliability of integrated circuits. Thermal stress in interconnects is determined by the thermal-mechanical properties of Cu lines, substrate, and dielectric materials. The effect of BEOL stacks on thermal stress characteristics of Cu lines were investigated using X-ray diffraction stress measurements. The stress characteristics of M1 and M4 level interconnects in full low-k and low-k/oxide hybrid dielectric stacks were evaluated, and the results indicated reduced substrate confinement and an increased impact of the dielectric material on in-plane stresses in higher level interconnects. The effects of dielectric stack and material properties were examined and the implication in the stresses of multilevel interconnects are discussed.

scholarly journals Introduction of Laser Pi-Grooving as Breakthrough Solution to Enhance die Strength of 40 nm ulow-k CMOS Silicon Technology during Wafer Saw Process

2021 ◽  
pp. 26-36
Author(s):  
Aiza Marie E. Agudon ◽  
Hynlie B. Inguin ◽  
Bryan Christian S. Bacquian
Keyword(s):  
Integrated Circuits ◽  
New Technologies ◽  
Process Development ◽  
Dielectric Material ◽  
Semiconductor Industry ◽  
Silicon Technology ◽  
Everyday Activities ◽  
New Process ◽  
Low K ◽  
Standard Laser

Nowadays, semiconductors and electronics are becoming part of our everyday activities. As the Integrated circuits become more useful to people, it also requires more function, which contain more complex and compact components. Aligned to this package requirement, the more challenging it become to package development as Silicon technology becomes more critical and complex from bare silicon to conventional MOS technology to Ultra Low-K, which requires a different strategy.  The new process development in the Semiconductor industry is a necessity to cope up with these new technologies. Low-k devices always pose a big challenge in achieving good dicing quality. This is because of the weak mechanical properties of the low-k dielectric material used.  Mechanical Sawing is the most popular cutting method for silicon, but with Ultra low-K technology, using mechanical sawing will lead to various sawing defects such as chippings and delamination [1,2]. These leads to the introduction of Laser Grooving to get rid of these dilemmas. Laser grooving uses heat to eradicate metals on this very thin metal wafer dicing saw streets in preparation for wafer saw process to prevent topside chippings and delamination/metal peel off [3]. These defects are not acceptable especially since the product application is a chip card. Since chip cards must be flexible and durable, they require higher die and package strength to serve its purpose. To achieve such package requirement, different method was evaluated such as standard mechanical dicing, standard Laser Grooving and the PI laser groove.   The paper will discuss how we were able to achieve the quality requirement for Ultra Low-K and at the same time eliminating top reject contributor during startup of this device.

Mechanical Properties of Porous MSQ Films: Impact of the Porogen Loading and Matrix Crosslinking.

2005 ◽  
Vol 863 ◽  
Author(s):  
F. Ciaramella ◽  
V. Jousseaume ◽  
S. Maitrejean ◽  
B. Rémiat ◽  
M. Verdier ◽  
...  
Keyword(s):  
Mechanical Properties ◽  
Integrated Circuits ◽  
Dielectric Material ◽  
Semiconductor Industry ◽  
Young Modulus ◽  
High Porosity ◽  
Porous Films ◽  
K Value ◽  
Porosity Level ◽  
Before And After

AbstractSemiconductor industry needs a continuously improvement of integrated circuits performance and an increase of integrated density on silicon. The 2004 ITRS Roadmap underlines the need of dielectric material for ILD with dielectric constant (k) lower than 3 for the 90 nm node and than 2.4 for the 45 nm node. In this work, porous films with k value lower than 2.2 were processed using a porogen approach. Firstly, a material composed of a methylsilsesquioxane (MSQ) matrix and of organic nanoparticles (called porogen) is deposited and baked. Then, this composite is thermally cured to allow the porogens degradation and matrix crosslinking. Different k values were obtained by varying the porogen loading in the composite. Mechanical properties of composite and porous films (before and after porogen removal respectively) were investigated using nanoindentation and FTIR analysis for different porogen loadings (between 0 and 40 %). The composite modulus is higher than the porous film modulus for high porogen loading. This result is interpreted in term of matrix crosslinking. Mechanical properties were also modelized using foam mechanical models. For high porosity level, the best Young modulus fitting is obtained with tetrakaidecaedric cells, which seems in good agreement with porosity morphology.

Mechanical Characterization of Multilayer Thin Film Stacks Containing Porous Silica Using Nanoindentation and the Finite Element Method

2005 ◽  
Vol 875 ◽  
Author(s):  
Ke Li ◽  
Subrahmanya Mudhivarthi ◽  
Sunil Saigal ◽  
Ashok Kumar
Keyword(s):  
Thin Film ◽  
Mechanical Properties ◽  
Dielectric Constant ◽  
Finite Element ◽  
Integrated Circuits ◽  
Dielectric Material ◽  
Porous Silica ◽  
Homogenization Method ◽  
Fe Model ◽  
Multilayer Thin Film

AbstractNovel metal/dielectric material combinations are becoming increasingly important for reducing the resistance-capacitance (RC) interconnection delay within integrated circuits (ICs) as the device dimensions shrink to the sub-micron scale. Copper (Cu) is the material of choice for metal interconnects and SiO2 (with a dielectric constant k = ∼ 3.9) has been used as an interlevel dielectric material in the industry. To meet the demands of the international road map for semiconductors, materials with a significantly lower dielectric constant are needed. In this study, the effects of porosity and layer thicknesses on the mechanical properties of a multilayer thin film (Cu, Ta and SiO2)-substrate (Si) system are examined using nanoindentation and finite element (FE) simulations. A micromechanics model is first developed to predict the stress-strain relation of the porous silica based on the homogenization method for composite materials. An FE model is then generated and validated to perform a parametric study on nanoindentation of the Cu/Ta/SiO2/Si system aiming to predict the mechanical properties of the multilayer film stack.

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