scholarly journals Bus Based Synchronization Method for CHIPPER Based NoC

2016 ◽  
Vol 2016 ◽  
pp. 1-11
Author(s):  
D. Muralidharan ◽  
R. Muthaiah
Keyword(s):  
Power Consumption ◽  
Network On Chip ◽  
System On Chip ◽  
Communication Delay ◽  
Worst Case ◽  
Synchronization Method ◽  
Area Overhead ◽  
On Chip

Network on Chip (NoC) reduces the communication delay of System on Chip (SoC). The main limitation of NoC is power consumption and area overhead. Bufferless NoC reduces the area complexity and power consumption by eliminating buffers in the traditional routers. The bufferless NoC design should include live lock freeness since they use hot potato routing. This increases the complexity of bufferless NoC design. Among the available propositions to reduce this complexity, CHIPPER based bufferless NoC is considered as one of the best options. Live lock freeness is provided in CHIPPER through golden epoch and golden packet. All routers follow some synchronization method to identify a golden packet. Clock based method is intuitively followed for synchronization in CHIPPER based NoCs. It is shown in this work that the worst-case latency of packets is unbearably high when the above synchronization is followed. To alleviate this problem, broadcast bus NoC (BBus NoC) approach is proposed in this work. The proposed method decreases the worst-case latency of packets by increasing the golden epoch rate of CHIPPER.

scholarly journals Low power network on chip architectures: A survey

2020 ◽  
Vol 2 (3) ◽  
pp. 158-168
Author(s):  
Muhammad Raza Naqvi
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Network Architecture ◽  
High Performance ◽  
State Of The Art ◽  
Network On Chip ◽  
System On Chip ◽  
Power Network ◽  
Network Routers ◽  
On Chip

Mostly communication now days is done through SoC (system on chip) models so, NoC (network on chip) architecture is most appropriate solution for better performance. However, one of major flaws in this architecture is power consumption. To gain high performance through this type of architecture it is necessary to confirm power consumption while designing this. Use of power should be diminished in every region of network chip architecture. Lasting power consumption can be lessened by reaching alterations in network routers and other devices used to form that network. This research mainly focusses on state-of-the-art methods for designing NoC architecture and techniques to reduce power consumption in those architectures like, network architecture, network links between nodes, network design, and routers.

Design of Router Supporting Multiply Routing Algorithm for NoC

2014 ◽  
Vol 981 ◽  
pp. 431-434
Author(s):  
Zhan Peng Jiang ◽  
Rui Xu ◽  
Chang Chun Dong ◽  
Lin Hai Cui
Keyword(s):  
Complex System ◽  
High Performance ◽  
Routing Algorithm ◽  
Network On Chip ◽  
System On Chip ◽  
Low Latency ◽  
Deterministic Routing ◽  
Key Features ◽  
Design Challenge ◽  
On Chip

Network on Chip(NoC)，a new proposed solution to solve global communication problem in complex System on Chip (SoC) design，has absorbed more and more researchers to do research in this area. Due to some distinct characteristics, NoC is different from both traditional off-chip network and traditional on-chip bus，and is facing with the huge design challenge. NoC router design is one of the most important issues in NoC system. The paper present a high-performance, low-latency two-stage pipelined router architecture suitable for NoC designs and providing a solution to irregular 2Dmesh topology for NoC. The key features of the proposed Mix Router are its suitability for 2Dmesh NoC topology and its capability of suorting both full-adaptive routing and deterministic routing algorithm.

scholarly journals Low Latency Network-on-Chip Router Microarchitecture Using Request Masking Technique

2015 ◽  
Vol 2015 ◽  
pp. 1-13 ◽  
Author(s):  
Alireza Monemi ◽  
Chia Yee Ooi ◽  
Muhammad Nadzir Marsono
Keyword(s):  
High Performance ◽  
Clock Cycle ◽  
Network On Chip ◽  
Operating Frequency ◽  
Low Latency ◽  
Core System ◽  
Low Area ◽  
Area Overhead ◽  
Logic Cells ◽  
On Chip

Network-on-Chip (NoC) is fast emerging as an on-chip communication alternative for many-core System-on-Chips (SoCs). However, designing a high performance low latency NoC with low area overhead has remained a challenge. In this paper, we present a two-clock-cycle latency NoC microarchitecture. An efficient request masking technique is proposed to combine virtual channel (VC) allocation with switch allocation nonspeculatively. Our proposed NoC architecture is optimized in terms of area overhead, operating frequency, and quality-of-service (QoS). We evaluate our NoC against CONNECT, an open source low latency NoC design targeted for field-programmable gate array (FPGA). The experimental results on several FPGA devices show that our NoC router outperforms CONNECT with 50% reduction of logic cells (LCs) utilization, while it works with 100% and 35%~20% higher operating frequency compared to the one- and two-clock-cycle latency CONNECT NoC routers, respectively. Moreover, the proposed NoC router achieves 2.3 times better performance compared to CONNECT.

scholarly journals Thermal-Aware Task Mapping on Dynamically Reconfigurable Network-on-Chip Based Multiprocessor System-on-Chip

2018 ◽  
Vol 67 (12) ◽  
pp. 1818-1834 ◽  
Author(s):  
Weichen Liu ◽  
Lei Yang ◽  
Weiwen Jiang ◽  
Liang Feng ◽  
Nan Guan ◽  
...  
Keyword(s):  
Network On Chip ◽  
System On Chip ◽  
Multiprocessor System ◽  
Task Mapping ◽  
Dynamically Reconfigurable ◽  
On Chip

3-D Mesh-Based Optical Network-on-Chip for Multiprocessor System-on-Chip

2013 ◽  
Vol 32 (4) ◽  
pp. 584-596 ◽  
Author(s):  
Yaoyao Ye ◽  
Jiang Xu ◽  
Baihan Huang ◽  
Xiaowen Wu ◽  
Wei Zhang ◽  
...  
Keyword(s):  
Optical Network ◽  
Network On Chip ◽  
System On Chip ◽  
Multiprocessor System ◽  
On Chip
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