scholarly journals Design and Implementation of Smart Non-Invasive Bone Conduction Ear-Plug System

Author(s):  
Ravichandran G ◽  
M Krishnamurthy

<p>The project aim is to design a smart earplug system integrated with non-invasive bone conduction technique which is capable of doing some advanced audio processing to provide voice enhancing, noise filtered audio for the hearing impaired people [2]. The system is also designed to work as an embedded music player, a life activity tracker and a Smartphone companion. It can even read the SMS that is just received on your smartphone into your ear. This project needs a very low power microcontroller but with high-performance signal processing requirements. STM32L476 from STMicroelectronics meets this needs and thus chosen as the main MCU. It is an ultra-low power ARM Cortex-M4 based microcontroller that can run up to 80MHz.  It has got 1MB of Flash memory and 128 KB RAM.</p>

Author(s):  
K. Hema ◽  
Muralidharan Muralidharan

<span lang="EN-IN">In this paper, we proposed to design a next-generation auto theft prevention system by adding significant enhancements and modernizing the existing security features</span><span lang="EN-IN">. </span><span lang="EN-IN">As vehicles turn out to be more refined, vehicle security frameworks must be more grounded than at any other time. A current vehicle uses remote keyless passage framework and Immobilizer framework as the primary weaponry against vehicle robbery. These structures avoid unapproved access of the vehicle to a particular degree, however, are not a secure one. Because of the straightforward and imperfect nature of these security frameworks, auto burglary occurrences worldwide are on the ascent. This venture needs a low power microcontroller however with elite prerequisites. LPC11C14 from NXP Semiconductors addresses these issues and in this manner picked as the primary MCU. It is an ultra-low-power ARM Cortex-M0 based microcontroller that can run up to 50MHz. It has 32KB of Flash memory and 8KB RAM. </span>


RSC Advances ◽  
2014 ◽  
Vol 4 (43) ◽  
pp. 22803-22807 ◽  
Author(s):  
Pranav Kumar Asthana ◽  
Bahniman Ghosh ◽  
Shiromani Bal Mukund Rahi ◽  
Yogesh Goswami

In this paper we have proposed an optimal design for a hetero-junctionless tunnel field effect transistor using HfO2 as a gate dielectric.


Micromachines ◽  
2020 ◽  
Vol 11 (2) ◽  
pp. 223 ◽  
Author(s):  
Yannan Zhang ◽  
Ke Han ◽  
and Jiawei Li

Ultra-low power and high-performance logical devices have been the driving force for the continued scaling of complementary metal oxide semiconductor field effect transistors which greatly enable electronic devices such as smart phones to be energy-efficient and portable. In the pursuit of smaller and faster devices, researchers and scientists have worked out a number of ways to further lower the leaking current of MOSFETs (Metal oxide semiconductor field effect transistor). Nanowire structure is now regarded as a promising candidate of future generation of logical devices due to its ultra-low off-state leaking current compares to FinFET. However, the potential of nanowire in terms of off-state current has not been fully discovered. In this article, a novel Core–Insulator Gate-All-Around (CIGAA) nanowire has been proposed, investigated, and simulated comprehensively and systematically based on 3D numerical simulation. Comparisons are carried out between GAA and CIGAA. The new CIGAA structure exhibits low off-state current compares to that of GAA, making it a suitable candidate of future low-power and energy-efficient devices.


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