scholarly journals Performance evaluation of GaN and Si based driver circuits for a SiC MOSFET power switch

Author(s):  
Martin J. Carra ◽  
Hernan Tacc ◽  
Jose Lipovetzky

<p>Silicon Carbide (SiC), new power switches (PSW) require new driver circuits which can take advantage of their new capabilities. In this paper a novel Gallium Nitride (GaN) based gate driver is proposed as a solution to control SiC power switches. The proposed driver is implemented and is performance compared with its silicon (Si) counterparts on a hard switching environment. A thorough evaluation of the energy involved in the switching process is presented showing that the GaN based circuit exhibits similar output losses but reduces the control power needed to operate at a specified frequency.</p>

2004 ◽  
Vol 815 ◽  
Author(s):  
Peter Friedrichs

AbstractCharge controlled power switching devices fabricated in 4H-Silicon Carbide are discussed in this paper. After comparing possible structures, results on prototype devices are presented. The presentation will give an overview about the developments of SiC power switches at SiCED, in addition some potential applications serving as an accelerator for the SiC power switch development will be sketched. The performance of vertical JFETs will be analyzed in detail. These can be operated as a single device as well as in combination with a low voltage silicon power MOSFET. The result of the hybrid assembly is a normally off device which behaves for the user more and more like a classical MOSFET with respect to the input as well as the output characteristic. Several improvements where performed which make the device more attractive for the customer. It will be shown which factors drive these optimization and how they can be implemented. Although the primary target for this device is the >1000V blocking voltage range, it will be discussed how the huge 600V power switch market can be made accessible for SiC power devices too. Intensively the high temperature performance of SiC JFETs and Si/SiC cascodes is discussed. Additionally, other developments like silicon power MOSFETs or high voltage switches will be mentioned.


AIP Advances ◽  
2021 ◽  
Vol 11 (7) ◽  
pp. 075013
Author(s):  
F. Meier ◽  
M. Protte ◽  
E. Baron ◽  
M. Feneberg ◽  
R. Goldhahn ◽  
...  

1971 ◽  
Vol 9 ◽  
pp. 158-164 ◽  
Author(s):  
D.K. Wickenden ◽  
K.R. Faulkner ◽  
R.W. Brander ◽  
B.J. Isherwood

2011 ◽  
Vol 20 (03) ◽  
pp. 471-484 ◽  
Author(s):  
LIANG ZUO ◽  
ROBERT GREENWELL ◽  
SYED K. ISLAM ◽  
M. A. HUQUE ◽  
BENJAMIN J. BLALOCK ◽  
...  

In recent years, increasing demand for hybrid electric vehicles (HEVs) has generated the need for reliable and low-cost high-temperature electronics which can operate at the high temperatures under the hood of these vehicles. A high-voltage and high temperature gate-driver integrated circuit for SiC FET switches with short circuit protection has been designed and implemented in a 0.8-micron silicon-on-insulator (SOI) high-voltage process. The prototype chip has been successfully tested up to 200°C ambient temperature without any heat sink or cooling mechanism. This gate-driver chip can drive SiC power FETs of the DC-DC converters in a HEV, and future chip modifications will allow it to drive the SiC power FETs of the traction drive inverter. The converter modules along with the gate-driver chip will be placed very close to the engine where the temperature can reach up to 175ΰC. Successful operation of the chip at this temperature with or without minimal heat sink and without liquid cooling will help achieve greater power-to-volume as well as power-to-weight ratios for the power electronics module.


2020 ◽  
Vol 2020 (1) ◽  
pp. 000015-000020
Author(s):  
Min Chu ◽  
Jie Chen ◽  
Abidur Rahman ◽  
Rajen Murugan

Abstract Generally, IC packages with exposed pads have excellent thermal and electrical performance – assuming high fidelity and integrity of die attach material. However, reliability challenges associated with die attach impacts electrical performance of vertical power FETs for high-side power switches. As such, it is critical to quantify the impact of these challenges on high-side power switches operation, so that their protection and diagnostic feature circuitries can be properly designed for mission critical applications. In this paper we present on a package and PCB co-modeling methodology that was developed to assess impact of die attach integrity on performance of high-side power switch designs. We explain how electrical co-optimization of the system (viz. FET-Package-PCB) interactions, was achieved through a coupled circuit-to-electromagnetic modeling, simulation, and analysis methodology. Silicon laboratory measurements data that validate the modeling methodology will be presented.


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