scholarly journals Modeling and Simulation of 127 Level Optimal Multilevel Inverter with Lower Number of Switches and Minimum THD

2018 ◽  
Vol 9 (4) ◽  
pp. 1765
Author(s):  
Bolla Madhusudana Reddy ◽  
Y. V. Siva Reddy ◽  
M. Vijaya Kumar
Keyword(s):  
Pulse Width Modulation ◽  
Harmonic Distortion ◽  
Multilevel Inverter ◽  
Basic Unit ◽  
Dc Voltage ◽  
Power Switches ◽  
Minimum Number ◽  
Current Production ◽  
Multi Level ◽  
High Level

<p><span lang="EN-US">This paper proposes a new optimal high level multilevel inverter with minimum number of components. This multi level inverter (MLI) is designed with series combination of basic units which can generate positive levels at output. DC source values applied for each basic unit is different with another. An H bridge is connected across proposed MLI for generating negative levels along with positive levels at output and that inverter considered as proposed high level optimal multilevel inverter. Single unit is responsible producing 21 levels. Therefore six units are connected in cascaded form to increase number of levels as 127 at output. Decrease in the number of power switches, driver circuits, and dc voltage sources are the improvement of the proposed MLI. Sinusoidal multiple pulse width modulation (SPWM) technique is implemented to produce pulses for turning ON switches according requirement. Low total harmonic distortion at output voltage or current production is major advantage of proposed module. The validations of proposed MLI results are verified through MATLAB/SIMULINK.</span></p>

scholarly journals Solar Photovoltaic System-Based Reduced Switch Multilevel Inverter for Improved Power Quality

2022 ◽  
Vol 4 (1) ◽  
pp. 1-13
Author(s):  
Madhu Andela ◽  
Ahmmadhussain Shaik ◽  
Saicharan Beemagoni ◽  
Vishal Kurimilla ◽  
Rajagopal Veramalla ◽  
...  
Keyword(s):  
Output Voltage ◽  
Pulse Width Modulation ◽  
Harmonic Distortion ◽  
Multilevel Inverter ◽  
Photovoltaic System ◽  
Solar Photovoltaic ◽  
Switching Losses ◽  
Minimum Number ◽  
Multi Level ◽  
Solar Photovoltaic System

This paper deals with a reduced switch multi-level inverter for the solar photovoltaic system-based 127-level multi-level inverter. The proposed technique uses the minimum number of switches to achieve the maximum steps in staircase AC output voltage when compared to the flying capacitor multi-level inverter, cascaded type multilevel inverter and diode clamped multi-level inverter. The use of a minimum number of switches decreases the cost of the system. To eliminate the switching losses, in this topology a square wave switch is used instead of pulse width modulation. Thereby the total harmonic distortion (THD) and harmonics have been reduced in the pulsating AC output voltage waveform. The performance of 127-level MLI is compared with 15 level, 31-level and 63-level multilevel inverters. The outcomes of the solar photovoltaic system-based 127-level multi-level inverter have been simulated in a MATLAB R2009b environment.

A Novel Generalized Topology for Multi-level Inverter with Switched Series-Parallel DC Sources

2016 ◽  
Vol 4 (1) ◽  
pp. 41 ◽  
Author(s):  
S. Sridhar ◽  
P. Satish Kumar ◽  
M. Susham
Keyword(s):  
Single Phase ◽  
Pulse Width Modulation ◽  
Electronic Devices ◽  
Software Tool ◽  
Multilevel Inverter ◽  
Power Electronic ◽  
Dc Voltage ◽  
Minimum Number ◽  
In Series ◽  
Multi Level

<p>This paper presents a novel topology of Single-phase multilevel inverter for low and high power applications. It consists of polarity (Level) generation circuit and H Bridge to generate both positive and negative polarities. The proposed topology can produce more output voltage levels by switching dc voltage sources in series and parallel. The proposed topology utilizes minimum number of power electronic devices which leads to the reduction of cost, size, and weight low and consumes low power which improves the efficiency. Switching pulses are generated using Phase disposition (PD) pulse width modulation technique. Finally the effectiveness of the proposed topology is verified using MATLAB/SIMULINK software tool. 7level asymmetrical multilevel inverter prototype hardware is prepared to support the proposed topology to verify the effectiveness and its validity.</p>

New Topology for Asymmetrical Multilevel Inverter: An Effort to Reduced Device Count

2017 ◽  
Vol 27 (04) ◽  
pp. 1850055 ◽  
Author(s):  
Kishor Thakre ◽  
Kanungo Barada Mohanty ◽  
Vinaya Sagar Kommukuri ◽  
Aditi Chatterjee
Keyword(s):  
Output Voltage ◽  
Pulse Width Modulation ◽  
Harmonic Distortion ◽  
Multilevel Inverter ◽  
Dc Voltage ◽  
Experimental Implementation ◽  
Voltage Stress ◽  
Power Switches ◽  
Driver Circuit ◽  
Gate Driver

Nowadays, multilevel inverters (MLI) are receiving remarkable attention due to salient features like less voltage stress on switches and low total harmonic distortion (THD) in output voltage. However, the required switch count increases with number of voltage levels. This paper presents a new topology for asymmetric multilevel inverter as a fundamental block. Each block generates 13-level output voltage using eight switches and four unequal dc voltage sources. The proposed configuration offers special features such as reduced number of switches, isolated dc sources, cost economy, less complex and modular structure than other similar contemporary topologies. Moreover, significant reduction in voltage stress on the circuit switches can be achieved. Comparative studies of proposed topology with the conventional and recent topologies have been presented in terms of power switches, gate driver circuit requirement, isolated dc voltage sources and total standing voltage. Multicarrier-based sinusoidal pulse width modulation (SPWM) scheme is adopted for generating switching signals using dSPACE real-time controller. In addition, proposed topology offers a fewer number of ON-state switches that lead to reduction in power loss. The proposed topology is validated through simulation and experimental implementation.

scholarly journals Simulation of Single Phase Switching Capacitor 49 Level Inverter with Reduced THD

2019 ◽  
Vol 8 (6) ◽  
pp. 837-841
Keyword(s):  
Power Supply ◽  
Single Phase ◽  
Harmonic Distortion ◽  
Matlab Simulation ◽  
Phase Switching ◽  
Dc Voltage ◽  
Dc Power ◽  
Power Switches ◽  
Multi Level ◽  
Switched Capacitor Converter

The study of single phase Switched Capacitors Multi Level Inverter (MLI) is used with Switched Capacitor Converter (SCC) units. The SCC is used to increase the input DC voltage by connecting capacitor in string and shunt. This increassed DC link voltage is converted in to multilevel i.e. 49 level AC output. This SCMLI topology is used to reduce the number of switches, diodes, isolated dc power supply and Total Harmonic Distortion (THD). The SCMLI provides 49 level output voltage using 14 power switches and 3 isolated power supply. The performance of the SCMLI topology is confirmed by using MATLAB simulation result

Component Count Reduced, Filter-Less H-Bridge Multilevel Inverter with Series and Parallel Connected Switches

2020 ◽  
pp. 2150052
Author(s):  
M Vijayakumar ◽  
S. M. Ramesh
Keyword(s):  
Pulse Width Modulation ◽  
Harmonic Distortion ◽  
Sine Wave ◽  
Multilevel Inverter ◽  
Level Shift ◽  
Modulation Scheme ◽  
Power Switching ◽  
Power Switches ◽  
Driver Circuit ◽  
Gate Driver

This paper introduces a new premium multilevel inverter (MLI) topology with cascaded H-Bridge and series-parallel connected switches to synthesize the fundamental sine wave with various levels of voltage. The component count is decreased by reducing the number of power switching devices, optoisolators, voltage gate drivers, snubber and filter circuits. The combination of two power switches and a separated DC (SDC) source is called an SDC module. Five SDC modules are required for a 63-level MLI and six SDC modules are required for a 127-level MLI. In this paper, both a 63-level and a 127-level filter-less single-phase MLIs are deliberated. The switches are controlled by employing a newer pulse width modulation (PWM) technique called periodic reduced digital carrier level shift PWM (PRDCLSPWM). As the number of levels increases to a greater extent, the total harmonic distortion diminishes without the need of filter circuit and the performance level also increases. Comparative analysis of proposed 63-level and 127-level MLIs topology with the conventional and modern topologies has been presented in terms of power switches, gate driver circuit requirement, DC voltage sources and THD limits. PRDCLSPWM scheme is derived and analyzed for the proposed 63-level and 127-level MLIs to eliminate low-order and high-order harmonics. Moreover, the performance of the proposed modulation scheme is compared with the most commonly used schemes. The modeling and simulation are done with MATLAB/SIMULINK 2016a.

scholarly journals Comparative Study of Total Harmonic Distortion in Multilevel Inverters Based WECS

2018 ◽  
Vol 7 (3.1) ◽  
pp. 42
Author(s):  
B Kandavel ◽  
G Uvaraj ◽  
M Manikandan
Keyword(s):  
Pulse Width ◽  
Pulse Width Modulation ◽  
Harmonic Distortion ◽  
Multilevel Inverter ◽  
Total Harmonic Distortion ◽  
Multilevel Inverters ◽  
Wind Speeds ◽  
Harmonic Content ◽  
Multi Level ◽  
Sinusoidal Pulse Width Modulation

This paper presents comparative study of Total Harmonic Distortion (THD) and its individual harmonic contents without grid and with grid for Diode clamped multi level inverter (DCMLI) and Flying capacitor clamped multilevel inverter (FCMLI) based Doubly Fed Induction Generator (DFIG) employing PI and Fuzzy logic controller (FLC). Simple method to control for a variable speed wind energy conversion system with a DFIG is connected to the grid through a diode rectifier and a diode clamped multilevel inverter (DCMLI). The DC-link voltage is controlled through a DC-DC boost converter to keep the DC voltage at constant value. Inverter is controlled by sinusoidal pulse width modulation technique, which supplies power to the grid. The THD and its harmonic content are studied for different wind speeds. DFIG fed flying capacitor multi level inverter (FCMLI) based WECS connected to load as well as grid. FCMLI is controlled through sinusoidal pulse width modulation. Voltage and current harmonics are studied. The results of both multilevel inverters are compared. It shows that the level of harmonic content of two types of multilevel inverters working at different wind speeds indicates that Total Harmonic Distortion (THD) for DCMLI has given best results.  

A Overlapping Carrier Based SPWM for a 5-Level Cascaded H-bridge Multilevel Inverter

2016 ◽  
Vol 1 (2) ◽  
pp. 221
Author(s):  
Kureve D. Teryima ◽  
Goshwe Y. Nentawe ◽  
Agbo O. David
Keyword(s):  
Pulse Width ◽  
Single Phase ◽  
Pulse Width Modulation ◽  
Harmonic Distortion ◽  
Switching Control ◽  
Multilevel Inverter ◽  
Total Harmonic Distortion ◽  
Control Technique ◽  
Control Techniques ◽  
Multi Level

<p>This paper proposes a switching control for a cascaded H-bridge inverter structure with reduced switches which is used to improve the THD performance of a single phase five level CHB MLI. The multi level inverter is simulated for the conventional carrier overlapping APOD and the proposed carrier overlapping APOD Pulse Width Modulation (PWM) switching control technique. The total harmonic distortion (THD) of the output voltages are observed for both PWM control techniques. The performance of the symmetric CHB MLI is simulated using MATLAB-SIMULINK. It is observed that the proposed carrier overlapping APODPWM provides output with relatively low THD as compared to the conventional carrier overlapping APODPWM.</p>

scholarly journals Energy transformation without using filter on high resistive load

2020 ◽  
Vol 40 (1) ◽  
pp. 39-42 ◽  
Author(s):  
Erol Can
Keyword(s):  
Pulse Width Modulation ◽  
Harmonic Distortion ◽  
Multilevel Inverter ◽  
Switching Function ◽  
Resistive Load ◽  
Energy Transformation ◽  
Operation Characteristic ◽  
Mathematical Equations ◽  
Ieee Standard ◽  
Multi Level

In this paper, 9-level, 17-level, 19-level, 21-level, 27-level, and 39- level inverters with SPWM are presented. According to a switching function, the high-multilevel inverter design has been described since a new multi-level inverter structure is considered. The multilevel inverter structure is designed with placing switches and sources on levels. Pulse width modulation, controlling switches in the inverter structure, is also produced by comparison between triangles and sinus signals. Operating sequences of the switches are given in the table in order to demonstrate the inverter operation characteristic with the produced signals. Then, mathematical equations are formed by considering an operation of switches on the load. In simulations and experiments, the 9-level, 17- level, 19-level, 21-level, 27-level, and 39-level inverters are performed on the resistance (R) and inductance (L) loads with different resistance, because it is difficult to generate current and voltage with an acceptable harmonic distortion on the impedances which have high ohmic values. After applications of experimentation and simulation, the obtained results are compared with other published papers of results and the international IEEE standard, which is 5% for harmonic distortions of creating currents and voltages.

scholarly journals Sinusoidal Pulse Width Modulation Based Speed Control of Induction Motor using Fifteen Level Diode Clamped Multilevel Inverter

2020 ◽  
Vol 9 (4) ◽  
pp. 2340-2345
Keyword(s):  
Induction Motor ◽  
Pulse Width Modulation ◽  
Harmonic Distortion ◽  
Speed Control ◽  
Multilevel Inverter ◽  
Motor Speed ◽  
Sine Curve ◽  
Driver Performance ◽  
Multi Level ◽  
Sinusoidal Pulse Width Modulation

The main purpose of this work is to use a fifteenstage diode clamped multi-level inverter that is able to control the speed of an induction motor. To get reduced synchronization and high quality sine curve output voltage. The proposed plan for the diode clamped multilevel inverter is controlled using multicarrier SPWM control. An open circle speed control can be accomplished by utilizing the V/ƒ strategy. This strategy can be executed by changing the recurrence utilized in the three-stage induction motor at the stock voltage and the consistent rate. The proposed system, which results in a poor driver performance, is a useful alternative to the conventional method with high transient losses. Simulation depicts an improved drive performance by reducing the Total Harmonic Distortion resulting from the simulation and effectively controlling the motor speed.

A Overlapping Carrier Based SPWM for a 5-Level Cascaded H-bridge Multilevel Inverter

2016 ◽  
Vol 7 (2) ◽  
pp. 349 ◽  
Author(s):  
Kureve D. Teryima ◽  
Goshwe Y. Nentawe ◽  
Agbo O. David
Keyword(s):  
Pulse Width ◽  
Single Phase ◽  
Pulse Width Modulation ◽  
Harmonic Distortion ◽  
Switching Control ◽  
Multilevel Inverter ◽  
Total Harmonic Distortion ◽  
Control Technique ◽  
Control Techniques ◽  
Multi Level

This paper proposes a switching control for a cascaded H-bridge inverter structure with reduced switches which is used to improve the THD performance of a single phase five level CHB MLI. The multi level inverter is simulated for the conventional carrier overlapping APOD and the proposed carrier overlapping APOD Pulse Width Modulation (PWM) switching control technique. The total harmonic distortion (THD) of the output voltages are observed for both PWM control techniques. The performance of the symmetric CHB MLI is simulated using MATLAB-SIMULINK. It is observed that the proposed carrier overlapping APODPWM provides output with relatively low THD as compared to the conventional carrier overlapping APODPWM.

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